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2016-12-27aspeed/scu: fix SCU region sizeCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-12-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: change SoC revision of the palmetto-bmc machineCédric Le Goater
The palmetto BMC machine uses a AST2400 revision A1 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-11-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add the definitions for the AST2400 A1 SoCCédric Le Goater
There is not much differences with the A0 revision apart from the DDR calibration. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add a memory region for SRAMCédric Le Goater
The size of the SRAM depends on the SoC model, so use a per-soc definition when creating the region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-9-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add support for the romulus-bmc boardCédric Le Goater
The Romulus machine is an OpenPOWER system with an AST2500 SoC for the BMC and a POWER9 chip for the host. It does not make much difference for qemu a part from the fact that the FMC controller has two SPI flash module. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 1480434248-27138-8-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: extend the board configuration with flash modelsCédric Le Goater
Future machine will use different flash models for the FMC and the SPI controllers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-7-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: attach the second SPI controller object to the SoCCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-6-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: remove cannot_destroy_with_object_finalize_yetCédric Le Goater
With commit ce5b1bbf624b ("exec: move cpu_exec_init() calls to realize functions"), we can now remove cannot_destroy_with_object_finalize_yet. Suggested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1480434248-27138-5-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: QOMify the CPU object and attach it to the SoCCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27m25p80: add support for the mx66l1g45gCédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27hw/arm/virt: add 2.9 machine typePeter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com>
2016-12-27hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPUPeter Maydell
The GICv3 requires that we only signal Pending interrupts to the CPU. This category does not include Pending+Active interrupts, which means we need to check whether the interrupt is Active in the gicr_int_pending() and gicd_int_pending() functions. Interrupts are rarely in the Active+Pending state, but KVM uses this as part of its handling of the virtual timer, so this bug was causing KVM to go into an infinite loop of taking the vtimer interrupt when the guest first triggered it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27hw/intc/arm_gicv3: Remove incorrect usage of fieldoffsetPeter Maydell
In the ARMCPRegInfo definitions for the GICv3 CPU interface registers, we were trying to use .fieldoffset to specify the locations of data fields within the GICv3CPUState struct. This is completely broken, because .fieldoffset is for offsets into the CPUARMState struct. We didn't notice because we were only using this for reads to BPR0, AP0R<n>, IGRPEN0 and CTLR_EL3, and Linux doesn't use these registers. Replace the .fieldoffset uses with explicit read functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27target-arm: Log AArch64 exception returnsPeter Maydell
We already log exception entry; add logging of the AArch64 exception return path as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27hw/intc/arm_gicv3_common: fix aff3 in typerAndrew Jones
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20161209143703.29457-1-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Fix aarch64 disas_ldst_single_structRichard Henderson
We add s->be_data within do_vec_ld/st. Adding it here means that we have the wrong bits set in SIZE for a big-endian host, leading to g_assert_not_reached in write_vec_element and read_vec_element. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-3-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Fix aarch64 vec_reg_offsetRichard Henderson
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27Correct value of ARM Cortex-A8 MVFR1 register.Julian Brown
The value of the MVFR1 (Media and VFP Feature Register 1) register for the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K), with the "full denormal arithmetic" and "propagation of NaN" fields holding both 0 instead of both 1. I had a go tracing the history of the use of this value, and it seems it's always just been wrong in QEMU: maybe it was derived from early documentation, or guessed based on the use of a "VFP Lite" implementation in the Cortex-A8. Depending on the startup/early-boot code in use, this can manifest as failure to perform denormal arithmetic properly: in our case, selecting a Cortex-A8 CPU when using QEMU as an instruction-set simulator for bare-metal GCC testing caused tests using denormal arithmetic to fail. Problems might be masked (or not occur) when using a full OS kernel with suitable trap handlers (I'm not sure). Signed-off-by: Julian Brown <julian@codesourcery.com> Message-id: 1481130858-31767-1-git-send-email-julian@codesourcery.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27cadence_uart: Check if receiver timeout counter is disabledAndrew Gacek
When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to 0, the receiver timeout counter should be disabled. See page 1801 of "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a such a check before setting the receive timeout interrupt. Signed-off-by: Andrew Gacek <andrew.gacek@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27cadence_uart: Check baud rate generator and divider values on migrationAlistair Francis
The Cadence UART device emulator calculates speed by dividing the baud rate by a 'baud rate generator' & 'baud rate divider' value. The device specification defines these register values to be non-zero and within certain limits. Checks were recently added when writing to these registers but not when restoring from migration. This patch adds checks when restoring from migration to avoid divide by zero errors. Reported-by: Huawei PSIRT <psirt@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 04ae30ed8ee1758cd2d2af880da4d28f74c67738.1481132150.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-22Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* core support for MemoryRegionCache from myself * rules.mak speedup and cleanups from myself and Marc-Adnré * multiboot command line fix from Vlad * SCSI fixes from myself * small qemu-timer speedup from myself * x86 debugging improvements from Doug * configurable Q35 devices from Chao * x86 5-level paging support from Kirill * x86 SHA_NI support for KVM from Yi Sun * improved kvmclock migration logic from Marcelo * bugfixes and doc fixes from others # gpg: Signature made Thu 22 Dec 2016 15:01:13 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (25 commits) x86: implement la57 paging mode target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns kvmclock: reduce kvmclock difference on migration kvm: sync linux headers scsi-disk: fix VERIFY for scsi-block hw/block/pflash_cfi*.c: fix confusing assert fail message multiboot: copy the cmdline verbatim, unescape module strings x86: Fix x86_64 'g' packet response to gdb from 32-bit mode. pc: make pit configurable pc: make sata configurable pc: make smbus configurable target-i386: Add Intel SHA_NI instruction support. block: drop remaining legacy aio functions in comment main-loop: update comment for qemu_mutex_lock/unlock_iothread timer: fix misleading comment in timer.h qemu-timer: check active_timers outside lock/event virtio-scsi: introduce virtio_scsi_acquire/release build-sys: remove libtool left-over rules.mak: add more rules to avoid chaining rules.mak: speedup save-vars load-vars ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-22Merge remote-tracking branch ↵Peter Maydell
'remotes/berrange/tags/pull-qcrypto-2016-12-21-2' into staging Merge qcrypto 2016/12/21 v2 # gpg: Signature made Thu 22 Dec 2016 10:46:17 GMT # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qcrypto-2016-12-21-2: crypto: add HMAC algorithms testcases crypto: support HMAC algorithms based on nettle crypto: support HMAC algorithms based on glib crypto: support HMAC algorithms based on libgcrypt crypto: add HMAC algorithms framework configure: add CONFIG_GCRYPT_HMAC item crypto: add 3des-ede support when using libgcrypt/nettle cipher: fix leak on initialization error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-22x86: implement la57 paging modeKirill A. Shutemov
The new paging more is extension of IA32e mode with more additional page table level. It brings support of 57-bit vitrual address space (128PB) and 52-bit physical address space (4PB). The structure of new page table level is identical to pml4. The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]. CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com> [Drop changes to target-i386/translate.c. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22target-i386: Fix eflags.TF/#DB handling of syscall/sysret insnsDoug Evans
The syscall and sysret instructions behave a bit differently: TF is checked after the instruction completes. This allows the o/s to disable #DB at a syscall by adding TF to FMASK. And then when the sysret is executed the #DB is taken "as if" the syscall insn just completed. Signed-off-by: Doug Evans <dje@google.com> Message-Id: <94eb2c0bfa1c6a9fec0543057483@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22kvmclock: reduce kvmclock difference on migrationMarcelo Tosatti
Check for KVM_CAP_ADJUST_CLOCK capability KVM_CLOCK_TSC_STABLE, which indicates that KVM_GET_CLOCK returns a value as seen by the guest at that moment. For new machine types, use this value rather than reading from guest memory. This reduces kvmclock difference on migration from 5s to 0.1s (when max_downtime == 5s). Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Message-Id: <20161121105052.598267440@redhat.com> [Add comment explaining what is going on. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22kvm: sync linux headersMarcelo Tosatti
Import KVM_CLOCK_TSC_STABLE. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Message-Id: <20161210172324.402794293@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22scsi-disk: fix VERIFY for scsi-blockPaolo Bonzini
When a scsi-disk object receives VERIFY command with BYTCHK bit being zero, scsi_block_is_passthrough returns false and finally makes req being proceeded by scsi_block_dma_command. Because scsi_block_dma_command has removed process of VERIFY, QEMU will abort in this function. Reported-by: Junlian Bell <zhongjun@sangfor.com.cn> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22hw/block/pflash_cfi*.c: fix confusing assert fail messageZiyue Yang
The patch is to fix the confusing assert fail message caused by un-initialized device structure (from bite sized tasks). The bug can be reproduced by ./qemu-system-x86_64 -nographic -device cfi.pflash01 The CFI hardware is dynamically loaded by QOM realizing mechanism, however the realizing function in pflash_cfi01_realize function requires the device being initialized manually before calling, like ./qemu-system-x86_64 -nographic -device cfi.pflash01,num-blocks=1024,sector-length=4096,name=testcard Once the initializing parameters are left off in the command, it will leave the device structure not initialized, which makes pflash_cfi01_realize try to realize a zero-volume card, causing /mnt/EXT_volume/projects/qemu/qemu-dev/exec.c:1378: find_ram_offset: Assertion `size != 0\' failed. Through my test, at least the flash device's block-number, sector-length and its name is needed for pflash_cfi01_realize to behave correctly. So I think the new asserts are needed to hint the QEMU user to specify the device's parameters correctly. Signed-off-by: Ziyue Yang <skiver.cloud.yzy@gmail.com> Message-Id: <1481810693-13733-1-git-send-email-skiver.cloud.yzy@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Ziyue Yang <yzylivezh@hotmail.com>
2016-12-22multiboot: copy the cmdline verbatim, unescape module stringsVlad Lungu
get_opt_value() truncates the value at the first comma Use memcpy() instead so that -append works correctly in the presence of commas. For -initrd to work right, instead, unescape the module filename and parameters with get_opt_value() before calling mb_add_cmdline(). Signed-off-by: Vlad Lungu <vlad.lungu@windriver.com> Message-Id: <1481805124-16242-1-git-send-email-vlad.lungu@windriver.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22x86: Fix x86_64 'g' packet response to gdb from 32-bit mode.Doug Evans
The remote protocol can't handle flipping back and forth between 32-bit and 64-bit regs. To compensate, pretend "as if" on 64-bit cpu when in 32-bit mode. Signed-off-by: Doug Evans <dje@google.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <001a113dca8274572005406e03c3@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22pc: make pit configurableChao Peng
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Message-Id: <1478330391-74060-4-git-send-email-chao.p.peng@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22pc: make sata configurableChao Peng
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Message-Id: <1478330391-74060-3-git-send-email-chao.p.peng@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22pc: make smbus configurableChao Peng
Signed-off-by: Chao Peng <chao.p.peng@linux.intel.com> Message-Id: <1478330391-74060-2-git-send-email-chao.p.peng@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22target-i386: Add Intel SHA_NI instruction support.Yi Sun
Add SHA_NI feature bit. Its spec can be found at: https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Signed-off-by: Yi Sun <yi.y.sun@linux.intel.com> Message-Id: <1481683803-10051-1-git-send-email-yi.y.sun@linux.intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22block: drop remaining legacy aio functions in commentYaowei Bai
Commit 87f68d318222563822b5c6b28192215fc4b4e441 (block: drop aio functions that operate on the main AioContext) drops qemu_aio_wait function references mostly while leaves these behind, clean up them. Signed-off-by: Yaowei Bai <baiyaowei@cmss.chinamobile.com> Message-Id: <1480566640-27264-3-git-send-email-baiyaowei@cmss.chinamobile.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22main-loop: update comment for qemu_mutex_lock/unlock_iothreadYaowei Bai
Commit 49cf57281b7 (vl: delay thread initialization after daemonization) makes the global mutex is taken after daemonization instead before daemonization by qemu_init_main_loop(). Signed-off-by: Yaowei Bai <baiyaowei@cmss.chinamobile.com> Message-Id: <1480566640-27264-2-git-send-email-baiyaowei@cmss.chinamobile.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22timer: fix misleading comment in timer.hYaowei Bai
It's timer to expire, not clock. Signed-off-by: Yaowei Bai <baiyaowei@cmss.chinamobile.com> Message-Id: <1480566640-27264-1-git-send-email-baiyaowei@cmss.chinamobile.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22qemu-timer: check active_timers outside lock/eventPaolo Bonzini
This avoids taking the active_timers_lock or resetting/setting the timers_done_ev if there are no active timers. This removes a small (2-3%) source of overhead for dataplane. The list is then checked again inside the lock, or a NULL pointer could be dereferenced. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22virtio-scsi: introduce virtio_scsi_acquire/releasePaolo Bonzini
These will be used more as soon as the acquire/release is pushed down to the ioeventfd handlers. Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22build-sys: remove libtool left-overMarc-André Lureau
Libtool support was removed in commit e999ee44349, there is a few left-over. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20161108070513.30274-1-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22rules.mak: add more rules to avoid chainingPaolo Bonzini
Really rule chaining is not a particularly expensive task, since GNU Make caches the directory listing. However it is easy to avoid it for most files and for phony targets (one was missing). After this patch, only "Makefile", "scripts/hxtool" and "scripts/create_config" attempt to use chained rules. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22rules.mak: speedup save-vars load-varsPaolo Bonzini
Unnesting variables spends a lot of time parsing and executing foreach and if functions. Because actually very few variables have to be saved and restored, a good strategy is to remember what has to be done in load-vars, and only iterate the right variables in load-vars. For save-vars, unroll the foreach loop to provide another small improvement. This speeds up a "noop" build from around 15.5 seconds on my laptop to 11.7 (25% roughly). Reviewed-by: Fam Zheng <famz@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22watchdog: 6300esb: add exit functionLi Qiang
When the Intel 6300ESB watchdog is hot unplug. The timer allocated in realize isn't freed thus leaking memory leak. This patch avoid this through adding the exit function. Signed-off-by: Li Qiang <liqiang6-s@360.cn> Message-Id: <583cde9c.3223ed0a.7f0c2.886e@mx.google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22exec: introduce MemoryRegionCachePaolo Bonzini
Device models often have to perform multiple access to a single memory region that is known in advance, but would to use "DMA-style" functions instead of address_space_map/unmap. This can happen for example when the data has to undergo endianness conversion. Introduce a new data structure to cache the result of address_space_translate without forcing usage of a host address like address_space_map does. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22exec: introduce address_space_extend_translationPaolo Bonzini
This extracts the common part of address_space_map and address_space_cache_init into a new function. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22exec: introduce memory_ldst.inc.cPaolo Bonzini
Templatize the address_space_* and *_phys functions, so that we can add similar functions in the next patch that work with a lightweight, cache-like version of address_space_map/unmap. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22exec: optimize remaining address_space_* casesPaolo Bonzini
Do them right before the next patch generalizes them into a multi-included file. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into ↵Peter Maydell
staging slirp updates # gpg: Signature made Tue 20 Dec 2016 23:05:13 GMT # gpg: using RSA key 0xA003196827414880 # gpg: Good signature from "Samuel Thibault <samuel.thibault@gnu.org>" # gpg: aka "Samuel Thibault <sthibault@debian.org>" # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@ens-lyon.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: 6B0F AC21 8566 46E9 4AA2 D200 A003 1968 2741 4880 * remotes/thibault/tags/samuel-thibault: slirp: support dynamic block size for TFTP transfers slirp, disas: Replace min/max with MIN/MAX macros Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-22crypto: add HMAC algorithms testcasesLongpeng(Mike)
This patch add HMAC algorithms testcases Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
2016-12-22crypto: support HMAC algorithms based on nettleLongpeng(Mike)
This patch add nettle-backed HMAC algorithms support Signed-off-by: Longpeng(Mike) <longpeng2@huawei.com> Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-14 19:25:11 +0000