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2016-03-30target-mips: make ITC Configuration Tags accessible to the CPULeon Alrae
Add CP0.ErrCtl register with WST, SPR and ITC bits. In 34K and interAptiv processors these bits are used to enable CACHE instruction access to different arrays. When WST=0, SPR=0 and ITC=1 the CACHE instruction will access ITC tag values. Generally we do not model caches and we have been treating the CACHE instruction as NOP. But since CACHE can operate on ITC Tags new MIPS_HFLAG_ITC_CACHE hflag is introduced to generate the helper only when CACHE is in the ITC Access mode. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30target-mips: check CP0 enabled for CACHE instruction also in R6Leon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - Bypass ViewLeon Alrae
Bypass View does not cause issuing thread to block and does not affect any of the cells state bit. Read from a FIFO cell returns the value of the oldest entry. Store to a FIFO cell changes the value of the newest entry. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - P/V Sync and Try ViewsLeon Alrae
P/V Synchronized and Try Views can be used to access Semaphore cells. Load returns current value and post-decrements the value in the cell (until it reaches zero). Stores increment the value (until it saturates at 0xFFFF). P/V Synchronized View causes the issuing thread to block on read if value is 0. P/V Try View does not block the thread, it returns 0 in this case. Cell's Empty and Full bits are not modified. Trap bit (i.e. Gating Storage exceptions) not implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - Empty/Full Sync and Try ViewsLeon Alrae
Empty/Full Synchronized and Try views can be used to access FIFO cells. Store to the FIFO cell pushes the value into the queue, load pops the oldest element from the queue. Cell's Full and Empty bits are automatically updated to reflect new state of the cell. Empty/Full Synchronized View causes the issuing thread to block when FIFO is empty while thread is performing a read, or FIFO is full while thread is performing a write. Empty/Full Try View never blocks the thread. If cell is full then write is ignored, if cell is empty then load returns 0. Trap bit (i.e. Gating Storage exceptions) not implemented. Store Conditional support for E/F Try View (i.e. indicate failure if FIFO is full) not implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Storage - Control ViewLeon Alrae
Control view is used to access the ITC Storage Cell Tags. It never causes the issuing thread to block. Guest can empty the FIFO cell by setting Empty bit to 1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement ITC Configuration Tags and Storage CellsLeon Alrae
Implement ITC as a single object consisting of two memory regions: 1) tag_io: ITC Configuration Tags (i.e. ITCAddressMap{0,1} registers) which are accessible by the CPU via CACHE instruction. Also adding MemoryRegion *itc_tag to the CPUMIPSState so that CACHE instruction will dispatch reads/writes directly. 2) storage_io: memory-mapped ITC Storage whose address space is configurable (i.e. enabled/remapped/resized) by writing to ITCAddressMap{0,1} registers. ITC Storage contains FIFO and Semaphore cells. Read-only FIFO bit in the ITC cell tag indicates the type of the cell. If the ITC Storage contains both types of cells then FIFOs are located before Semaphores. Since issuing thread can get blocked on the access to a cell (in E/F Synchronized and P/V Synchronized Views) each cell has a bitmap to track which threads are currently blocked. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30target-mips: enable CM GCR in MIPS64R6-generic CPULeon Alrae
Indicate that in the MIPS64R6-generic CPU the memory-mapped Global Configuration Register Space is implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: add CPS to Malta boardLeon Alrae
If the user specifies smp > 1 and the CPU with CM GCR support, then create Coherent Processing System (which takes care of instantiating CPUs) rather than CPUs directly and connect i8259 and cbus to the pins exposed by CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use the same pin numbers as before. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: move CPU creation to a separate functionLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: remove redundant irq and clock initLeon Alrae
Global smp_cpus is never zero (even if user provides -smp 0), thus clocks and irqs are always initialized for each created CPU in the loop at the beginning of mips_malta_init. These two lines cause a leak of already allocated timer and irqs for the first CPU - remove them. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips_malta: remove CPUMIPSState from the write_bootloader()Leon Alrae
Remove CPUMIPSState from the write_bootloader() argument list as it is not used in the function. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips/cps: create CPC block inside CPSLeon Alrae
Create Cluster Power Controller and add a link to the CPC MemoryRegion in GCR. Guest can enable / map CPC to any physical address by writing to the memory-mapped GCR_CPC_BASE register. Set vp-start-reset property to 1 to allow only first VP to run from reset. Others are brought up by the guest via CPC memory-mapped registers. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: add initial Cluster Power Controller supportLeon Alrae
Cluster Power Controller (CPC) is responsible for power management in multiprocessing system. It provides registers to control the power and the clock frequency of the individual elements in the system. This patch implements only three registers that are used to control the power state of each VP on a single core: * VP Run is a write-only register used to set each VP to the run state * VP Stop is a write-only register used to set each VP to the suspend state * VP Running is a read-only register indicating the run state of each VP Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips/cps: create GCR block inside CPSLeon Alrae
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: add initial Global Config Register supportYongbok Kim
Add initial GCR support to indicate number of VPs present in the system, L2 bypass mode and revision number. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: * removed GIC part, * changed commit message, * replaced %lx format spec. with PRIx64, * renamed mips_gcr.{c,h} to mips_cmgcr.{c,h}, * replaced CONFIG_MIPS_GIC with CONFIG_MIPS_CPS] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30target-mips: add CMGCRBase registerYongbok Kim
Physical base address for the memory-mapped Coherency Manager Global Configuration Register space. The MIPS default location for the GCR_BASE address is 0x1FBF_8. This register only exists if Config3 CMGCR is set to one. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: move CMGCR enabling to a separate patch] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-30hw/mips: implement generic MIPS Coherent Processing System containerLeon Alrae
Implement generic MIPS Coherent Processing System (CPS) which in this commit just creates VPs, but it will serve as a container also for other components like Global Configuration Registers and Cluster Power Controller. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
2016-03-29Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into stagingPeter Maydell
# gpg: Signature made Tue 29 Mar 2016 01:48:09 BST using RSA key ID C0DE3057 # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>" # gpg: aka "Jeffrey Cody <jeff@codyprime.org>" # gpg: aka "Jeffrey Cody <codyprime@gmail.com>" * remotes/cody/tags/block-pull-request: qemu-iotests: add no-op streaming test qemu-iotests: fix test_stream_partial() block: never cancel a streaming job without running stream_complete() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-29Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into ↵Peter Maydell
staging slirp updates # gpg: Signature made Tue 29 Mar 2016 00:16:05 BST using RSA key ID FB6B2F1D # gpg: Good signature from "Samuel Thibault <samuel.thibault@gnu.org>" # gpg: aka "Samuel Thibault <sthibault@debian.org>" # gpg: aka "Samuel Thibault <samuel.thibault@inria.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@labri.fr>" # gpg: aka "Samuel Thibault <samuel.thibault@ens-lyon.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 900C B024 B679 31D4 0F82 304B D017 8C76 7D06 9EE6 # Subkey fingerprint: F632 74CD C630 0873 CB3D 29D9 E3E5 1CE8 FB6B 2F1D * remotes/thibault/tags/samuel-thibault: Rework ipv6 options Use C99 flexible array instead of 1-byte trailing array Avoid embedding struct mbuf in other structures slirp: send icmp6 errors when UDP send failed slirp: Fix memory leak on small incoming ipv4 packet Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-29Merge remote-tracking branch 'remotes/awilliam/tags/vfio-update-20160328.0' ↵Peter Maydell
into staging VFIO updates 2016-03-28 - Use 128bit math to avoid asserts with IOMMU regions (Bandan Das) # gpg: Signature made Mon 28 Mar 2016 23:16:52 BST using RSA key ID 3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" # gpg: aka "Alex Williamson <alex@shazbot.org>" # gpg: aka "Alex Williamson <alwillia@redhat.com>" # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" * remotes/awilliam/tags/vfio-update-20160328.0: vfio: convert to 128 bit arithmetic calculations when adding mem regions Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-29Rework ipv6 optionsSamuel Thibault
Rename the recently-added ip6-foo options into ipv6-foo options, to make them coherent with other ipv6 options. Also rework the documentation. Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org> Reviewed-by: Eric Blake <eblake@redhat.com>
2016-03-29Use C99 flexible array instead of 1-byte trailing arrayPeter Maydell
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Samuel Thibault <samuel.thibault@ens-lyon.org>
2016-03-28vfio: convert to 128 bit arithmetic calculations when adding mem regionsBandan Das
vfio_listener_region_add for a iommu mr results in an overflow assert since iommu memory region is initialized with UINT64_MAX. Convert calculations to 128 bit arithmetic for iommu memory regions and let int128_get64 assert for non iommu regions if there's an overflow. Suggested-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bandan Das <bsd@redhat.com> [missed (end - 1) on 2nd trace call, move llsize closer to use] Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2016-03-28qemu-iotests: add no-op streaming testAlberto Garcia
This patch tests that in a partial block-stream operation, no data is ever copied from the base image. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 5272a2aa57bc0b3f981f8b3e0c813e58a88c974b.1458566441.git.berto@igalia.com Signed-off-by: Jeff Cody <jcody@redhat.com>
2016-03-28qemu-iotests: fix test_stream_partial()Alberto Garcia
This test is streaming to the top layer using the intermediate image as the base. This is a mistake since block-stream never copies data from the base image and its backing chain, so this is effectively a no-op. In addition to fixing the base parameter, this patch also writes some data to the intermediate image before the test, so there's something to copy and the test is meaningful. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Message-id: 2efa304da38b32d47c120ce728568a589c5a3afc.1458566441.git.berto@igalia.com Signed-off-by: Jeff Cody <jcody@redhat.com>
2016-03-28block: never cancel a streaming job without running stream_complete()Alberto Garcia
We need to call stream_complete() in order to do all the necessary clean-ups, even if there's an early failure. At the moment it's only useful to make sure that s->backing_file_str is not leaked, but it will become more important if we introduce support for streaming to any intermediate node. Signed-off-by: Alberto Garcia <berto@igalia.com> Reviewed-by: Max Reitz <mreitz@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 2abedf2debc65c250560237f31a8e6756883c8fc.1458566441.git.berto@igalia.com Signed-off-by: Jeff Cody <jcody@redhat.com>
2016-03-24Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell
* Log filtering from Alex and Peter * Chardev fix from Marc-André * config.status tweak from David * Header file tweaks from Markus, myself and Veronia (Outreachy candidate) * get_ticks_per_sec() removal from Rutuja (Outreachy candidate) * Coverity fix from myself * PKE implementation from myself, based on rth's XSAVE support # gpg: Signature made Thu 24 Mar 2016 20:15:11 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" * remotes/bonzini/tags/for-upstream: (28 commits) target-i386: implement PKE for TCG config.status: Pass extra parameters char: translate from QIOChannel error to errno exec: fix error handling in file_ram_alloc cputlb: modernise the debug support qemu-log: support simple pid substitution for logs target-arm: dfilter support for in_asm qemu-log: dfilter-ise exec, out_asm, op and opt_op qemu-log: new option -dfilter to limit output qemu-log: Improve the "exec" TB execution logging qemu-log: Avoid function call for disabled qemu_log_mask logging qemu-log: correct help text for -d cpu tcg: pass down TranslationBlock to tcg_code_gen util: move declarations out of qemu-common.h Replaced get_tick_per_sec() by NANOSECONDS_PER_SECOND hw: explicitly include qemu-common.h and cpu.h include/crypto: Include qapi-types.h or qemu/bswap.h instead of qemu-common.h isa: Move DMA_transfer_handler from qemu-common.h to hw/isa/isa.h Move ParallelIOArg from qemu-common.h to sysemu/char.h Move QEMU_ALIGN_*() from qemu-common.h to qemu/osdep.h ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Conflicts: scripts/clean-includes
2016-03-24Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20160324' into stagingPeter Maydell
Support for booting from virtio-scsi devices in the s390-ccw bios. # gpg: Signature made Thu 24 Mar 2016 08:14:21 GMT using RSA key ID C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" * remotes/cohuck/tags/s390x-20160324: s390-ccw.img: rebuild image pc-bios/s390-ccw: disambiguation of "No zIPL magic" message pc-bios/s390-ccw: enhance bootmap detection pc-bios/s390-ccw: enable virtio-scsi pc-bios/s390-ccw: add virtio-scsi implementation pc-bios/s390-ccw: add scsi definitions pc-bios/s390-ccw: add simplified virtio call pc-bios/s390-ccw: make provisions for different backends pc-bios/s390-ccw: add vdev object to store all device details pc-bios/s390-ccw: update virtio implementation to allow up to 3 vrings pc-bios/s390-ccw: qemuize types pc-bios/s390-ccw: add utility functions and "export" some others pc-bios/s390-ccw: virtio_panic -> panic pc-bios/s390-ccw: add more disk layout checks Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-24Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20160324-1' into ↵Peter Maydell
staging input-linux + spice fixes # gpg: Signature made Thu 24 Mar 2016 07:54:45 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-ui-20160324-1: spice: Disallow use of gl + TCP port input-linux: fix Coverity warning input-linux: switch over to -object Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-24Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.6-20160324' ↵Peter Maydell
into staging ppc patch queue for 2016-03-24 Accumulated patches for target-ppc, pseries machine type and related devices. * Preliminary patches from BenH & Cédric Le Goater's powernv code * We don't want the full machine type before 2.7 * Adding some of the SPRs also fixes migration corner cases for spapr (when qemu has no knowledge of the registers, they're obviously not migrated) * We include some patches that aren't strictly fixes, but make applying the others easier, and they're low risk * Fix to buffer management which significantly improves throughput in the spapr-llan virtual network device * Start with 64-bit mode enabled on spapr. This is the way it's supposed to be but we broke it a while back and didn't notice because Linux guests cope anyway. * Picked up by kvm-unit-tests * Still some bugs here that I'm working on # gpg: Signature made Thu 24 Mar 2016 04:29:42 GMT using RSA key ID 20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.6-20160324: ppc: move POWER8 Book4 regs in their own routine hw/net/spapr_llan: Enable the RX buffer pools by default for new machines hw/net/spapr_llan: Fix receive buffer handling for better performance hw/net/spapr_llan: Extract rx buffer code into separate functions ppc: A couple more dummy POWER8 Book4 regs ppc: Add dummy CIABR SPR ppc: Add POWER8 IAMR register ppc: Fix writing to AMR/UAMOR ppc: Initialize AMOR in PAPR mode ppc: Add dummy SPR_IC for POWER8 ppc: Create cpu_ppc_set_papr() helper ppc: Add a bunch of hypervisor SPRs to Book3s ppc: Add macros to register hypervisor mode SPRs ppc: Update SPR definitions spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it ppc64: set MSR_SF bit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-24Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160323' into stagingPeter Maydell
MIPS patches 2016-03-23 Changes: * add mips-softmmu-common.mak * indicate presence of IEEE 754-2008 FPU in MIPS64R6-generic and P5600 # gpg: Signature made Wed 23 Mar 2016 16:38:04 GMT using RSA key ID 0B29DA6B # gpg: Good signature from "Leon Alrae <leon.alrae@imgtec.com>" * remotes/lalrae/tags/mips-20160323: default-configs: add mips-softmmu-common.mak target-mips: indicate presence of IEEE 754-2008 FPU in R6/R5+MSA CPUs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-24Merge remote-tracking branch 'remotes/pmaydell/tags/pull-cocoa-20160323-1' ↵Peter Maydell
into staging cocoa queue: * update cocoa UI front end to use QKeyCodes * fix the help menu documentation links to actually work (with both an installed and an uninstalled QEMU) # gpg: Signature made Wed 23 Mar 2016 14:31:01 GMT using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" * remotes/pmaydell/tags/pull-cocoa-20160323-1: ui/cocoa.m: switch to QKeyCode qapi-schema.json: Add power and keypad equal keys ui/cocoa.m: fix help menus Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-24target-i386: implement PKE for TCGPaolo Bonzini
Tested with kvm-unit-tests. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-24config.status: Pass extra parametersDr. David Alan Gilbert
This allows you to do: ./config.status --the-option-you-forgot Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <1452599928-7471-1-git-send-email-dgilbert@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-03-24Merge remote-tracking branch ↵Peter Maydell
'remotes/bkoppelmann/tags/pull-tricore-20160323' into staging TriCore FPU + bugfixes # gpg: Signature made Wed 23 Mar 2016 08:26:03 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20160323: target-tricore: Add ftoi and itof instructions target-tricore: Add cmp.f instruction target-tricore: Add div.f instruction target-tricore: Add mul.f instruction target-tricore: add add.f/sub.f instructions target-tricore: Move general CHECK_REG_PAIR of decode_rrr_divide target-tricore: Add FPU infrastructure target-tricore: Fix psw_read() clearing too many bits target-tricore: Fix helper_msub64_q_ssov not reseting OVF bit target-tricore: add missing break in insn decode switch stmt Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-03-24spice: Disallow use of gl + TCP portChristophe Fergeau
Currently, virgl support has to go through a local unix socket, trying to connect to a VM using -spice gl through spice://localhost:5900 will only result in a black screen. This commit errors out when the user tries to start a VM with both GL support and a port/tls-port set. This would fit better in spice-server, but currently QEMU does not call into spice-server when parsing 'gl' on its command line, so we have to do this check in QEMU instead. Signed-off-by: Christophe Fergeau <cfergeau@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1457955672-28758-1-git-send-email-cfergeau@redhat.com [ applied codestyle fix: break long line ] Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2016-03-24input-linux: fix Coverity warningGerd Hoffmann
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 1458129049-12484-1-git-send-email-kraxel@redhat.com
2016-03-24input-linux: switch over to -objectGerd Hoffmann
This patches makes input-linux use -object instead of a new command line switch. So, instead of the switch ... -input-linux /dev/input/event$nr ... you must create an object this way: -object input-linux,id=$name,evdev=/dev/input/event$nr Bonus is that you can hot-add and hot-remove them via monitor now. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1457681901-30916-1-git-send-email-kraxel@redhat.com
2016-03-24ppc: move POWER8 Book4 regs in their own routineCédric Le Goater
commit fce55481360d "ppc: A couple more dummy POWER8 Book4 regs" squashed in to rapidly a set of POWER8 Book4 regs in the wrong routine. This patch introduces the missing gen_spr_power8_book4() routine to fix their location. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24hw/net/spapr_llan: Enable the RX buffer pools by default for new machinesThomas Huth
RX buffer pools are now enabled by default for new machine types. For older machine types, they are still disabled to avoid breaking migration. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24hw/net/spapr_llan: Fix receive buffer handling for better performanceThomas Huth
tl;dr: This patch introduces an alternate way of handling the receive buffers of the spapr-vlan device, resulting in much better receive performance for the guest. Full story: One of our testers recently discovered that the performance of the spapr-vlan device is very poor compared to other NICs, and that a simple "ping -i 0.2 -s 65507 someip" in the guest can result in more than 50% lost ping packets (especially with older guest kernels < 3.17). After doing some analysis, it was clear that there is a problem with the way we handle the receive buffers in spapr_llan.c: The ibmveth driver of the guest Linux kernel tries to add a lot of buffers into several buffer pools (with 512, 2048 and 65536 byte sizes by default, but it can be changed via the entries in the /sys/devices/vio/1000/pool* directories of the guest). However, the spapr-vlan device of QEMU only tries to squeeze all receive buffer descriptors into one single page which has been supplied by the guest during the H_REGISTER_LOGICAL_LAN call, without taking care of different buffer sizes. This has two bad effects: First, only a very limited number of buffer descriptors is accepted at all. Second, we also hand 64k buffers to the guest even if the 2k buffers would fit better - and this results in dropped packets in the IP layer of the guest since too much skbuf memory is used. Though it seems at a first glance like PAPR says that we should store the receive buffer descriptors in the page that is supplied during the H_REGISTER_LOGICAL_LAN call, chapter 16.4.1.2 in the LoPAPR spec declares that "the contents of these descriptors are architecturally opaque, none of these descriptors are manipulated by code above the architected interfaces". That means we don't have to store the RX buffer descriptors in this page, but can also manage the receive buffers at the hypervisor level only. This is now what we are doing here: Introducing proper RX buffer pools which are also sorted by size of the buffers, so we can hand out a buffer with the best fitting size when a packet has been received. To avoid problems with migration from/to older version of QEMU, the old behavior is also retained and enabled by default. The new buffer management has to be enabled via a new "use-rx-buffer-pools" property. Now with the new buffer pool management enabled, the problem with "ping -s 65507" is fixed for me, and the throughput of a simple test with wget increases from creeping 3MB/s up to 20MB/s! Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24hw/net/spapr_llan: Extract rx buffer code into separate functionsThomas Huth
Refactor the code a little bit by extracting the code that reads and writes the receive buffer list page into separate functions. There should be no functional change in this patch, this is just a preparation for the upcoming extensions that introduce receive buffer pools. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: A couple more dummy POWER8 Book4 regsBenjamin Herrenschmidt
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: squashed in patch 'ppc: Add dummy ACOP SPR' ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: Add dummy CIABR SPRBenjamin Herrenschmidt
We should implement HW breakpoint/watchpoint, qemu supports them... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: Add POWER8 IAMR registerBenjamin Herrenschmidt
With appropriate AMR-like masks. Not actually used by the translation logic at that point Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: changed spr_register_hv(SPR_IAMR) to spr_register_kvm_hv(SPR_IAMR) changed gen_spr_amr() prototype ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: Fix writing to AMR/UAMORBenjamin Herrenschmidt
The masks weren't chosen nor applied properly. The architecture specifies that writes to AMR are masked by UAMOR for PR=1, otherwise AMOR for HV=0. The writes to UAMOR are masked by AMOR for HV=0 Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [clg: moved gen_spr_amr() prototype change to next patch ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: Initialize AMOR in PAPR modeBenjamin Herrenschmidt
Make sure we give the guest full authorization Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: Add dummy SPR_IC for POWER8Benjamin Herrenschmidt
It's supposed to be an instruction counter. For now make us not crash when accessing it. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2016-03-24ppc: Create cpu_ppc_set_papr() helperBenjamin Herrenschmidt
And move the code adjusting the MSR mask and calling kvmppc_set_papr() to it. This allows us to add a few more things such as disabling setting of MSR:HV and appropriate LPCR bits which will be used when fixing the exception model. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [clg: removed LPCR setting ] Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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