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-rw-r--r--target/mips/cpu-qom.h4
-rw-r--r--target/mips/cpu.c12
2 files changed, 10 insertions, 6 deletions
diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index e28b529607..0dffab453b 100644
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -34,7 +34,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
/**
* MIPSCPUClass:
* @parent_realize: The parent class' realize handler.
- * @parent_reset: The parent class' reset handler.
+ * @parent_phases: The parent class' reset phase handlers.
*
* A MIPS CPU model.
*/
@@ -44,7 +44,7 @@ struct MIPSCPUClass {
/*< public >*/
DeviceRealize parent_realize;
- DeviceReset parent_reset;
+ ResettablePhases parent_phases;
const struct mips_def_t *cpu_def;
/* Used for the jazz board to modify mips_cpu_do_transaction_failed. */
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 7a565466cb..c614b04607 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -182,14 +182,16 @@ static bool mips_cpu_has_work(CPUState *cs)
#include "cpu-defs.c.inc"
-static void mips_cpu_reset(DeviceState *dev)
+static void mips_cpu_reset_hold(Object *obj)
{
- CPUState *cs = CPU(dev);
+ CPUState *cs = CPU(obj);
MIPSCPU *cpu = MIPS_CPU(cs);
MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
CPUMIPSState *env = &cpu->env;
- mcc->parent_reset(dev);
+ if (mcc->parent_phases.hold) {
+ mcc->parent_phases.hold(obj);
+ }
memset(env, 0, offsetof(CPUMIPSState, end_reset_fields));
@@ -562,10 +564,12 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
CPUClass *cc = CPU_CLASS(c);
DeviceClass *dc = DEVICE_CLASS(c);
+ ResettableClass *rc = RESETTABLE_CLASS(c);
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
- device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
+ resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
+ &mcc->parent_phases);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;