diff options
Diffstat (limited to 'target-sparc/translate.c')
| -rw-r--r-- | target-sparc/translate.c | 1044 |
1 files changed, 521 insertions, 523 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index d2188a040e..77fb72396d 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -31,6 +31,9 @@ #include "helper.h" #include "tcg-op.h" +#define GEN_HELPER 1 +#include "helper.h" + #define DEBUG_DISAS #define DYNAMIC_PC 1 /* dynamic pc value */ @@ -38,25 +41,30 @@ according to jump_pc[T2] */ /* global register indexes */ -static TCGv cpu_env, cpu_regwptr; +static TCGv_ptr cpu_env, cpu_regwptr; static TCGv cpu_cc_src, cpu_cc_src2, cpu_cc_dst; -static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; +static TCGv_i32 cpu_psr; +static TCGv cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8]; static TCGv cpu_y; #ifndef CONFIG_USER_ONLY static TCGv cpu_tbr; #endif static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val; #ifdef TARGET_SPARC64 -static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr; +static TCGv_i32 cpu_xcc, cpu_asi, cpu_fprs; +static TCGv cpu_gsr; static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr; -static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, cpu_softint; +static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver; +static TCGv_i32 cpu_softint; #else static TCGv cpu_wim; #endif /* local register indexes (only used inside old micro ops) */ -static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64; +static TCGv cpu_tmp0; +static TCGv_i32 cpu_tmp32; +static TCGv_i64 cpu_tmp64; /* Floating point registers */ -static TCGv cpu_fpr[TARGET_FPREGS]; +static TCGv_i32 cpu_fpr[TARGET_FPREGS]; #include "gen-icount.h" @@ -239,28 +247,28 @@ static inline void gen_goto_tb(DisasContext *s, int tb_num, } // XXX suboptimal -static inline void gen_mov_reg_N(TCGv reg, TCGv src) +static inline void gen_mov_reg_N(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_shri_tl(reg, reg, PSR_NEG_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } -static inline void gen_mov_reg_Z(TCGv reg, TCGv src) +static inline void gen_mov_reg_Z(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_shri_tl(reg, reg, PSR_ZERO_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } -static inline void gen_mov_reg_V(TCGv reg, TCGv src) +static inline void gen_mov_reg_V(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_shri_tl(reg, reg, PSR_OVF_SHIFT); tcg_gen_andi_tl(reg, reg, 0x1); } -static inline void gen_mov_reg_C(TCGv reg, TCGv src) +static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src) { tcg_gen_extu_i32_tl(reg, src); tcg_gen_shri_tl(reg, reg, PSR_CARRY_SHIFT); @@ -292,7 +300,7 @@ static inline void gen_cc_NZ_icc(TCGv dst) l1 = gen_new_label(); l2 = gen_new_label(); - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL); tcg_gen_brcondi_tl(TCG_COND_NE, r_temp, 0, l1); tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO); @@ -330,8 +338,8 @@ static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1) int l1; l1 = gen_new_label(); - r_temp1 = tcg_temp_new(TCG_TYPE_TL); - r_temp2 = tcg_temp_new(TCG_TYPE_TL); + r_temp1 = tcg_temp_new(); + r_temp2 = tcg_temp_new(); tcg_gen_andi_tl(r_temp1, dst, 0xffffffffULL); tcg_gen_andi_tl(r_temp2, src1, 0xffffffffULL); tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); @@ -361,7 +369,7 @@ static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp; - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_xor_tl(r_temp, src1, src2); tcg_gen_not_tl(r_temp, r_temp); tcg_gen_xor_tl(cpu_tmp0, src1, dst); @@ -378,7 +386,7 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp; - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_xor_tl(r_temp, src1, src2); tcg_gen_not_tl(r_temp, r_temp); tcg_gen_xor_tl(cpu_tmp0, src1, dst); @@ -393,12 +401,13 @@ static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2) static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) { - TCGv r_temp, r_const; + TCGv r_temp; + TCGv_i32 r_const; int l1; l1 = gen_new_label(); - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_xor_tl(r_temp, src1, src2); tcg_gen_not_tl(r_temp, r_temp); tcg_gen_xor_tl(cpu_tmp0, src1, dst); @@ -406,8 +415,8 @@ static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2) tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); r_const = tcg_const_i32(TT_TOVF); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); gen_set_label(l1); tcg_temp_free(r_temp); } @@ -427,15 +436,15 @@ static inline void gen_cc_V_tag(TCGv src1, TCGv src2) static inline void gen_tag_tv(TCGv src1, TCGv src2) { int l1; - TCGv r_const; + TCGv_i32 r_const; l1 = gen_new_label(); tcg_gen_or_tl(cpu_tmp0, src1, src2); tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1); r_const = tcg_const_i32(TT_TOVF); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); gen_set_label(l1); } @@ -529,8 +538,8 @@ static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2) int l1; l1 = gen_new_label(); - r_temp1 = tcg_temp_new(TCG_TYPE_TL); - r_temp2 = tcg_temp_new(TCG_TYPE_TL); + r_temp1 = tcg_temp_new(); + r_temp2 = tcg_temp_new(); tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL); tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL); tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1); @@ -560,7 +569,7 @@ static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp; - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_xor_tl(r_temp, src1, src2); tcg_gen_xor_tl(cpu_tmp0, src1, dst); tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); @@ -576,7 +585,7 @@ static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) { TCGv r_temp; - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_xor_tl(r_temp, src1, src2); tcg_gen_xor_tl(cpu_tmp0, src1, dst); tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); @@ -590,20 +599,21 @@ static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2) static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2) { - TCGv r_temp, r_const; + TCGv r_temp; + TCGv_i32 r_const; int l1; l1 = gen_new_label(); - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); tcg_gen_xor_tl(r_temp, src1, src2); tcg_gen_xor_tl(cpu_tmp0, src1, dst); tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0); tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 31)); tcg_gen_brcondi_tl(TCG_COND_EQ, r_temp, 0, l1); r_const = tcg_const_i32(TT_TOVF); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); gen_set_label(l1); tcg_temp_free(r_temp); } @@ -694,7 +704,7 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) int l1; l1 = gen_new_label(); - r_temp = tcg_temp_new(TCG_TYPE_TL); + r_temp = tcg_temp_new(); /* old op: if (!(env->y & 1)) @@ -740,10 +750,10 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2) static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) { - TCGv r_temp, r_temp2; + TCGv_i64 r_temp, r_temp2; - r_temp = tcg_temp_new(TCG_TYPE_I64); - r_temp2 = tcg_temp_new(TCG_TYPE_I64); + r_temp = tcg_temp_new_i64(); + r_temp2 = tcg_temp_new_i64(); tcg_gen_extu_tl_i64(r_temp, src2); tcg_gen_extu_tl_i64(r_temp2, src1); @@ -751,22 +761,22 @@ static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2) tcg_gen_shri_i64(r_temp, r_temp2, 32); tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); - tcg_temp_free(r_temp); + tcg_temp_free_i64(r_temp); tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); #ifdef TARGET_SPARC64 tcg_gen_mov_i64(dst, r_temp2); #else tcg_gen_trunc_i64_tl(dst, r_temp2); #endif - tcg_temp_free(r_temp2); + tcg_temp_free_i64(r_temp2); } static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) { - TCGv r_temp, r_temp2; + TCGv_i64 r_temp, r_temp2; - r_temp = tcg_temp_new(TCG_TYPE_I64); - r_temp2 = tcg_temp_new(TCG_TYPE_I64); + r_temp = tcg_temp_new_i64(); + r_temp2 = tcg_temp_new_i64(); tcg_gen_ext_tl_i64(r_temp, src2); tcg_gen_ext_tl_i64(r_temp2, src1); @@ -774,27 +784,27 @@ static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2) tcg_gen_shri_i64(r_temp, r_temp2, 32); tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp); - tcg_temp_free(r_temp); + tcg_temp_free_i64(r_temp); tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff); #ifdef TARGET_SPARC64 tcg_gen_mov_i64(dst, r_temp2); #else tcg_gen_trunc_i64_tl(dst, r_temp2); #endif - tcg_temp_free(r_temp2); + tcg_temp_free_i64(r_temp2); } #ifdef TARGET_SPARC64 static inline void gen_trap_ifdivzero_tl(TCGv divisor) { - TCGv r_const; + TCGv_i32 r_const; int l1; l1 = gen_new_label(); tcg_gen_brcondi_tl(TCG_COND_NE, divisor, 0, l1); r_const = tcg_const_i32(TT_DIV_ZERO); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); gen_set_label(l1); } @@ -849,13 +859,13 @@ static inline void gen_op_eval_ba(TCGv dst) } // Z -static inline void gen_op_eval_be(TCGv dst, TCGv src) +static inline void gen_op_eval_be(TCGv dst, TCGv_i32 src) { gen_mov_reg_Z(dst, src); } // Z | (N ^ V) -static inline void gen_op_eval_ble(TCGv dst, TCGv src) +static inline void gen_op_eval_ble(TCGv dst, TCGv_i32 src) { gen_mov_reg_N(cpu_tmp0, src); gen_mov_reg_V(dst, src); @@ -865,7 +875,7 @@ static inline void gen_op_eval_ble(TCGv dst, TCGv src) } // N ^ V -static inline void gen_op_eval_bl(TCGv dst, TCGv src) +static inline void gen_op_eval_bl(TCGv dst, TCGv_i32 src) { gen_mov_reg_V(cpu_tmp0, src); gen_mov_reg_N(dst, src); @@ -873,7 +883,7 @@ static inline void gen_op_eval_bl(TCGv dst, TCGv src) } // C | Z -static inline void gen_op_eval_bleu(TCGv dst, TCGv src) +static inline void gen_op_eval_bleu(TCGv dst, TCGv_i32 src) { gen_mov_reg_Z(cpu_tmp0, src); gen_mov_reg_C(dst, src); @@ -881,13 +891,13 @@ static inline void gen_op_eval_bleu(TCGv dst, TCGv src) } // C -static inline void gen_op_eval_bcs(TCGv dst, TCGv src) +static inline void gen_op_eval_bcs(TCGv dst, TCGv_i32 src) { gen_mov_reg_C(dst, src); } // V -static inline void gen_op_eval_bvs(TCGv dst, TCGv src) +static inline void gen_op_eval_bvs(TCGv dst, TCGv_i32 src) { gen_mov_reg_V(dst, src); } @@ -899,20 +909,20 @@ static inline void gen_op_eval_bn(TCGv dst) } // N -static inline void gen_op_eval_bneg(TCGv dst, TCGv src) +static inline void gen_op_eval_bneg(TCGv dst, TCGv_i32 src) { gen_mov_reg_N(dst, src); } // !Z -static inline void gen_op_eval_bne(TCGv dst, TCGv src) +static inline void gen_op_eval_bne(TCGv dst, TCGv_i32 src) { gen_mov_reg_Z(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !(Z | (N ^ V)) -static inline void gen_op_eval_bg(TCGv dst, TCGv src) +static inline void gen_op_eval_bg(TCGv dst, TCGv_i32 src) { gen_mov_reg_N(cpu_tmp0, src); gen_mov_reg_V(dst, src); @@ -923,7 +933,7 @@ static inline void gen_op_eval_bg(TCGv dst, TCGv src) } // !(N ^ V) -static inline void gen_op_eval_bge(TCGv dst, TCGv src) +static inline void gen_op_eval_bge(TCGv dst, TCGv_i32 src) { gen_mov_reg_V(cpu_tmp0, src); gen_mov_reg_N(dst, src); @@ -932,7 +942,7 @@ static inline void gen_op_eval_bge(TCGv dst, TCGv src) } // !(C | Z) -static inline void gen_op_eval_bgu(TCGv dst, TCGv src) +static inline void gen_op_eval_bgu(TCGv dst, TCGv_i32 src) { gen_mov_reg_Z(cpu_tmp0, src); gen_mov_reg_C(dst, src); @@ -941,21 +951,21 @@ static inline void gen_op_eval_bgu(TCGv dst, TCGv src) } // !C -static inline void gen_op_eval_bcc(TCGv dst, TCGv src) +static inline void gen_op_eval_bcc(TCGv dst, TCGv_i32 src) { gen_mov_reg_C(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !N -static inline void gen_op_eval_bpos(TCGv dst, TCGv src) +static inline void gen_op_eval_bpos(TCGv dst, TCGv_i32 src) { gen_mov_reg_N(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); } // !V -static inline void gen_op_eval_bvc(TCGv dst, TCGv src) +static inline void gen_op_eval_bvc(TCGv dst, TCGv_i32 src) { gen_mov_reg_V(dst, src); tcg_gen_xori_tl(dst, dst, 0x1); @@ -1207,7 +1217,7 @@ static inline void gen_op_next_insn(void) static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond) { - TCGv r_src; + TCGv_i32 r_src; #ifdef TARGET_SPARC64 if (cc) @@ -1467,144 +1477,168 @@ static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn, } } -static GenOpFunc * const gen_fcmpd[4] = { - helper_fcmpd, - helper_fcmpd_fcc1, - helper_fcmpd_fcc2, - helper_fcmpd_fcc3, -}; - -static GenOpFunc * const gen_fcmpq[4] = { - helper_fcmpq, - helper_fcmpq_fcc1, - helper_fcmpq_fcc2, - helper_fcmpq_fcc3, -}; - -static GenOpFunc * const gen_fcmped[4] = { - helper_fcmped, - helper_fcmped_fcc1, - helper_fcmped_fcc2, - helper_fcmped_fcc3, -}; - -static GenOpFunc * const gen_fcmpeq[4] = { - helper_fcmpeq, - helper_fcmpeq_fcc1, - helper_fcmpeq_fcc2, - helper_fcmpeq_fcc3, -}; - -static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) +static inline void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { case 0: - tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2); + gen_helper_fcmps(r_rs1, r_rs2); break; case 1: - tcg_gen_helper_0_2(helper_fcmps_fcc1, r_rs1, r_rs2); + gen_helper_fcmps_fcc1(r_rs1, r_rs2); break; case 2: - tcg_gen_helper_0_2(helper_fcmps_fcc2, r_rs1, r_rs2); + gen_helper_fcmps_fcc2(r_rs1, r_rs2); break; case 3: - tcg_gen_helper_0_2(helper_fcmps_fcc3, r_rs1, r_rs2); + gen_helper_fcmps_fcc3(r_rs1, r_rs2); break; } } static inline void gen_op_fcmpd(int fccno) { - tcg_gen_helper_0_0(gen_fcmpd[fccno]); + switch (fccno) { + case 0: + gen_helper_fcmpd(); + break; + case 1: + gen_helper_fcmpd_fcc1(); + break; + case 2: + gen_helper_fcmpd_fcc2(); + break; + case 3: + gen_helper_fcmpd_fcc3(); + break; + } } static inline void gen_op_fcmpq(int fccno) { - tcg_gen_helper_0_0(gen_fcmpq[fccno]); + switch (fccno) { + case 0: + gen_helper_fcmpq(); + break; + case 1: + gen_helper_fcmpq_fcc1(); + break; + case 2: + gen_helper_fcmpq_fcc2(); + break; + case 3: + gen_helper_fcmpq_fcc3(); + break; + } } -static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) +static inline void gen_op_fcmpes(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2) { switch (fccno) { case 0: - tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2); + gen_helper_fcmpes(r_rs1, r_rs2); break; case 1: - tcg_gen_helper_0_2(helper_fcmpes_fcc1, r_rs1, r_rs2); + gen_helper_fcmpes_fcc1(r_rs1, r_rs2); break; case 2: - tcg_gen_helper_0_2(helper_fcmpes_fcc2, r_rs1, r_rs2); + gen_helper_fcmpes_fcc2(r_rs1, r_rs2); break; case 3: - tcg_gen_helper_0_2(helper_fcmpes_fcc3, r_rs1, r_rs2); + gen_helper_fcmpes_fcc3(r_rs1, r_rs2); break; } } static inline void gen_op_fcmped(int fccno) { - tcg_gen_helper_0_0(gen_fcmped[fccno]); + switch (fccno) { + case 0: + gen_helper_fcmped(); + break; + case 1: + gen_helper_fcmped_fcc1(); + break; + case 2: + gen_helper_fcmped_fcc2(); + break; + case 3: + gen_helper_fcmped_fcc3(); + break; + } } static inline void gen_op_fcmpeq(int fccno) { - tcg_gen_helper_0_0(gen_fcmpeq[fccno]); + switch (fccno) { + case 0: + gen_helper_fcmpeq(); + break; + case 1: + gen_helper_fcmpeq_fcc1(); + break; + case 2: + gen_helper_fcmpeq_fcc2(); + break; + case 3: + gen_helper_fcmpeq_fcc3(); + break; + } } #else static inline void gen_op_fcmps(int fccno, TCGv r_rs1, TCGv r_rs2) { - tcg_gen_helper_0_2(helper_fcmps, r_rs1, r_rs2); + gen_helper_fcmps(r_rs1, r_rs2); } static inline void gen_op_fcmpd(int fccno) { - tcg_gen_helper_0_0(helper_fcmpd); + gen_helper_fcmpd(); } static inline void gen_op_fcmpq(int fccno) { - tcg_gen_helper_0_0(helper_fcmpq); + gen_helper_fcmpq(); } static inline void gen_op_fcmpes(int fccno, TCGv r_rs1, TCGv r_rs2) { - tcg_gen_helper_0_2(helper_fcmpes, r_rs1, r_rs2); + gen_helper_fcmpes(r_rs1, r_rs2); } static inline void gen_op_fcmped(int fccno) { - tcg_gen_helper_0_0(helper_fcmped); + gen_helper_fcmped(); } static inline void gen_op_fcmpeq(int fccno) { - tcg_gen_helper_0_0(helper_fcmpeq); + gen_helper_fcmpeq(); } #endif static inline void gen_op_fpexception_im(int fsr_flags) { - TCGv r_const; + TCGv_i32 r_const; tcg_gen_andi_tl(cpu_fsr, cpu_fsr, FSR_FTT_NMASK); tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags); r_const = tcg_const_i32(TT_FP_EXCP); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); } static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond) { #if !defined(CONFIG_USER_ONLY) if (!dc->fpu_enabled) { - TCGv r_const; + TCGv_i32 r_const; save_state(dc, r_cond); r_const = tcg_const_i32(TT_NFPU_INSN); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); dc->is_br = 1; return 1; } @@ -1619,18 +1653,18 @@ static inline void gen_op_clear_ieee_excp_and_FTT(void) static inline void gen_clear_float_exceptions(void) { - tcg_gen_helper_0_0(helper_clear_float_exceptions); + gen_helper_clear_float_exceptions(); } /* asi moves */ #ifdef TARGET_SPARC64 -static inline TCGv gen_get_asi(int insn, TCGv r_addr) +static inline TCGv_i32 gen_get_asi(int insn, TCGv r_addr) { int asi; - TCGv r_asi; + TCGv_i32 r_asi; if (IS_IMM) { - r_asi = tcg_temp_new(TCG_TYPE_I32); + r_asi = tcg_temp_new_i32(); tcg_gen_mov_i32(r_asi, cpu_asi); } else { asi = GET_FIELD(insn, 19, 26); @@ -1642,115 +1676,116 @@ static inline TCGv gen_get_asi(int insn, TCGv r_addr) static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign) { - TCGv r_asi, r_size, r_sign; + TCGv_i32 r_asi, r_size, r_sign; r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(size); r_sign = tcg_const_i32(sign); - tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi, r_size, r_sign); - tcg_temp_free(r_sign); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); + gen_helper_ld_asi(dst, addr, r_asi, r_size, r_sign); + tcg_temp_free_i32(r_sign); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); } static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) { - TCGv r_asi, r_size; + TCGv_i32 r_asi, r_size; r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(size); - tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, r_size); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); + gen_helper_st_asi(addr, src, r_asi, r_size); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); } static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd) { - TCGv r_asi, r_size, r_rd; + TCGv_i32 r_asi, r_size, r_rd; r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(size); r_rd = tcg_const_i32(rd); - tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, r_size, r_rd); - tcg_temp_free(r_rd); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); + gen_helper_ldf_asi(addr, r_asi, r_size, r_rd); + tcg_temp_free_i32(r_rd); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); } static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd) { - TCGv r_asi, r_size, r_rd; + TCGv_i32 r_asi, r_size, r_rd; r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(size); r_rd = tcg_const_i32(rd); - tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, r_size, r_rd); - tcg_temp_free(r_rd); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); + gen_helper_stf_asi(addr, r_asi, r_size, r_rd); + tcg_temp_free_i32(r_rd); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); } static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) { - TCGv r_asi, r_size, r_sign; + TCGv_i32 r_asi, r_size, r_sign; r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(4); r_sign = tcg_const_i32(0); - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); - tcg_temp_free(r_sign); - tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); + gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); + tcg_temp_free_i32(r_sign); + gen_helper_st_asi(addr, dst, r_asi, r_size); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); tcg_gen_trunc_i64_tl(dst, cpu_tmp64); } static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) { - TCGv r_asi, r_rd; + TCGv_i32 r_asi, r_rd; r_asi = gen_get_asi(insn, addr); r_rd = tcg_const_i32(rd); - tcg_gen_helper_0_3(helper_ldda_asi, addr, r_asi, r_rd); - tcg_temp_free(r_rd); - tcg_temp_free(r_asi); + gen_helper_ldda_asi(addr, r_asi, r_rd); + tcg_temp_free_i32(r_rd); + tcg_temp_free_i32(r_asi); } static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) { - TCGv r_asi, r_size; + TCGv_i32 r_asi, r_size; gen_movl_reg_TN(rd + 1, cpu_tmp0); tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); r_asi = gen_get_asi(insn, addr); r_size = tcg_const_i32(8); - tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); + gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); } static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd) { - TCGv r_val1, r_asi; + TCGv r_val1; + TCGv_i32 r_asi; - r_val1 = tcg_temp_new(TCG_TYPE_TL); + r_val1 = tcg_temp_new(); gen_movl_reg_TN(rd, r_val1); r_asi = gen_get_asi(insn, addr); - tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi); - tcg_temp_free(r_asi); + gen_helper_cas_asi(dst, addr, r_val1, val2, r_asi); + tcg_temp_free_i32(r_asi); tcg_temp_free(r_val1); } static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd) { - TCGv r_asi; + TCGv_i32 r_asi; gen_movl_reg_TN(rd, cpu_tmp64); r_asi = gen_get_asi(insn, addr); - tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi); - tcg_temp_free(r_asi); + gen_helper_casx_asi(dst, addr, cpu_tmp64, val2, r_asi); + tcg_temp_free_i32(r_asi); } #elif !defined(CONFIG_USER_ONLY) @@ -1758,12 +1793,12 @@ static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign) { - TCGv r_asi, r_size, r_sign; + TCGv_i32 r_asi, r_size, r_sign; r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(size); r_sign = tcg_const_i32(sign); - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); + gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); tcg_temp_free(r_sign); tcg_temp_free(r_size); tcg_temp_free(r_asi); @@ -1772,26 +1807,30 @@ static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size) { - TCGv r_asi, r_size; + TCGv_i32 r_asi, r_size; tcg_gen_extu_tl_i64(cpu_tmp64, src); r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(size); - tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); + gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); tcg_temp_free(r_size); tcg_temp_free(r_asi); } static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) { - TCGv r_asi, r_size, r_sign; + TCGv_i32 r_asi, r_size, r_sign; + TCGv_i64 r_val; r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(4); r_sign = tcg_const_i32(0); - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); + gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); tcg_temp_free(r_sign); - tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi, r_size); + r_val = tcg_temp_new_i64(); + tcg_gen_extu_tl_i64(r_val, dst); + gen_helper_st_asi(addr, r_val, r_asi, r_size); + tcg_temp_free_i64(r_val); tcg_temp_free(r_size); tcg_temp_free(r_asi); tcg_gen_trunc_i64_tl(dst, cpu_tmp64); @@ -1799,12 +1838,12 @@ static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn) static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) { - TCGv r_asi, r_size, r_sign; + TCGv_i32 r_asi, r_size, r_sign; r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(8); r_sign = tcg_const_i32(0); - tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi, r_size, r_sign); + gen_helper_ld_asi(cpu_tmp64, addr, r_asi, r_size, r_sign); tcg_temp_free(r_sign); tcg_temp_free(r_size); tcg_temp_free(r_asi); @@ -1817,13 +1856,13 @@ static inline void gen_ldda_asi(TCGv hi, TCGv addr, int insn, int rd) static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) { - TCGv r_asi, r_size; + TCGv_i32 r_asi, r_size; gen_movl_reg_TN(rd + 1, cpu_tmp0); tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, hi); r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(8); - tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi, r_size); + gen_helper_st_asi(addr, cpu_tmp64, r_asi, r_size); tcg_temp_free(r_size); tcg_temp_free(r_asi); } @@ -1832,17 +1871,18 @@ static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd) #if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn) { - TCGv r_val, r_asi, r_size; + TCGv_i64 r_val; + TCGv_i32 r_asi, r_size; gen_ld_asi(dst, addr, insn, 1, 0); r_val = tcg_const_i64(0xffULL); r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26)); r_size = tcg_const_i32(1); - tcg_gen_helper_0_4(helper_st_asi, addr, r_val, r_asi, r_size); - tcg_temp_free(r_size); - tcg_temp_free(r_asi); - tcg_temp_free(r_val); + gen_helper_st_asi(addr, r_val, r_asi, r_size); + tcg_temp_free_i32(r_size); + tcg_temp_free_i32(r_asi); + tcg_temp_free_i64(r_val); } #endif @@ -1900,8 +1940,8 @@ static void disas_sparc_insn(DisasContext * dc) rd = GET_FIELD(insn, 2, 6); - cpu_src1 = tcg_temp_new(TCG_TYPE_TL); // const - cpu_src2 = tcg_temp_new(TCG_TYPE_TL); // const + cpu_src1 = tcg_temp_new(); // const + cpu_src2 = tcg_temp_new(); // const switch (opc) { case 0: /* branches/sethi */ @@ -2028,9 +2068,10 @@ static void disas_sparc_insn(DisasContext * dc) else tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); - tcg_gen_helper_0_1(raise_exception, cpu_dst); + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); + gen_helper_raise_exception(cpu_tmp32); } else if (cond != 0) { - TCGv r_cond = tcg_temp_new(TCG_TYPE_TL); + TCGv r_cond = tcg_temp_new(); int l1; #ifdef TARGET_SPARC64 /* V9 icc/xcc */ @@ -2056,7 +2097,8 @@ static void disas_sparc_insn(DisasContext * dc) else tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK); tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP); - tcg_gen_helper_0_1(raise_exception, cpu_dst); + tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst); + gen_helper_raise_exception(cpu_tmp32); gen_set_label(l1); tcg_temp_free(r_cond); @@ -2083,7 +2125,7 @@ static void disas_sparc_insn(DisasContext * dc) break; #ifdef TARGET_SPARC64 case 0x2: /* V9 rdccr */ - tcg_gen_helper_1_0(helper_rdccr, cpu_dst); + gen_helper_rdccr(cpu_dst); gen_movl_TN_reg(rd, cpu_dst); break; case 0x3: /* V9 rdasi */ @@ -2092,14 +2134,13 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x4: /* V9 rdtick */ { - TCGv r_tickptr; + TCGv_ptr r_tickptr; - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, tick)); - tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, - r_tickptr); - tcg_temp_free(r_tickptr); + gen_helper_tick_get_count(cpu_dst, r_tickptr); + tcg_temp_free_ptr(r_tickptr); gen_movl_TN_reg(rd, cpu_dst); } break; @@ -2132,14 +2173,13 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x18: /* System tick */ { - TCGv r_tickptr; + TCGv_ptr r_tickptr; - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, stick)); - tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst, - r_tickptr); - tcg_temp_free(r_tickptr); + gen_helper_tick_get_count(cpu_dst, r_tickptr); + tcg_temp_free_ptr(r_tickptr); gen_movl_TN_reg(rd, cpu_dst); } break; @@ -2160,7 +2200,7 @@ static void disas_sparc_insn(DisasContext * dc) #ifndef TARGET_SPARC64 if (!supervisor(dc)) goto priv_insn; - tcg_gen_helper_1_0(helper_rdpsr, cpu_dst); + gen_helper_rdpsr(cpu_dst); #else CHECK_IU_FEATURE(dc, HYPV); if (!hypervisor(dc)) @@ -2199,64 +2239,63 @@ static void disas_sparc_insn(DisasContext * dc) switch (rs1) { case 0: // tpc { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); - tcg_gen_ld_tl(cpu_tmp32, r_tsptr, + tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc)); - tcg_temp_free(r_tsptr); - tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); + tcg_temp_free_ptr(r_tsptr); } break; case 1: // tnpc { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnpc)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); } break; case 2: // tstate { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_ld_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); } break; case 3: // tt { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); - tcg_gen_ld_i32(cpu_tmp0, r_tsptr, + tcg_gen_ld_i32(cpu_tmp32, r_tsptr, offsetof(trap_state, tt)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); + tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); } break; case 4: // tick { - TCGv r_tickptr; + TCGv_ptr r_tickptr; - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, tick)); - tcg_gen_helper_1_1(helper_tick_get_count, cpu_tmp0, - r_tickptr); + gen_helper_tick_get_count(cpu_tmp0, r_tickptr); gen_movl_TN_reg(rd, cpu_tmp0); - tcg_temp_free(r_tickptr); + tcg_temp_free_ptr(r_tickptr); } break; case 5: // tba @@ -2278,7 +2317,7 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_ext_i32_tl(cpu_tmp0, cpu_tmp32); break; case 9: // cwp - tcg_gen_helper_1_0(helper_rdcwp, cpu_tmp0); + gen_helper_rdcwp(cpu_tmp0); break; case 10: // cansave tcg_gen_ld_i32(cpu_tmp32, cpu_env, @@ -2332,7 +2371,7 @@ static void disas_sparc_insn(DisasContext * dc) } else if (xop == 0x2b) { /* rdtbr / V9 flushw */ #ifdef TARGET_SPARC64 save_state(dc, cpu_cond); - tcg_gen_helper_0_0(helper_flushw); + gen_helper_flushw(); #else if (!supervisor(dc)) goto priv_insn; @@ -2352,50 +2391,47 @@ static void disas_sparc_insn(DisasContext * dc) tcg_gen_mov_i32(cpu_fpr[rd], cpu_fpr[rs2]); break; case 0x5: /* fnegs */ - tcg_gen_helper_1_1(helper_fnegs, cpu_fpr[rd], - cpu_fpr[rs2]); + gen_helper_fnegs(cpu_fpr[rd], cpu_fpr[rs2]); break; case 0x9: /* fabss */ - tcg_gen_helper_1_1(helper_fabss, cpu_fpr[rd], - cpu_fpr[rs2]); + gen_helper_fabss(cpu_fpr[rd], cpu_fpr[rs2]); break; case 0x29: /* fsqrts */ CHECK_FPU_FEATURE(dc, FSQRT); gen_clear_float_exceptions(); - tcg_gen_helper_1_1(helper_fsqrts, cpu_tmp32, - cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsqrts(cpu_tmp32, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0x2a: /* fsqrtd */ CHECK_FPU_FEATURE(dc, FSQRT); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fsqrtd); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsqrtd(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x2b: /* fsqrtq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fsqrtq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsqrtq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0x41: /* fadds */ gen_clear_float_exceptions(); - tcg_gen_helper_1_2(helper_fadds, cpu_tmp32, - cpu_fpr[rs1], cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fadds(cpu_tmp32, + cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0x42: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_faddd); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_faddd(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x43: /* faddq */ @@ -2403,23 +2439,23 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_faddq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_faddq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0x45: /* fsubs */ gen_clear_float_exceptions(); - tcg_gen_helper_1_2(helper_fsubs, cpu_tmp32, - cpu_fpr[rs1], cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsubs(cpu_tmp32, + cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0x46: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fsubd); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsubd(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x47: /* fsubq */ @@ -2427,16 +2463,16 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fsubq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsubq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0x49: /* fmuls */ CHECK_FPU_FEATURE(dc, FMUL); gen_clear_float_exceptions(); - tcg_gen_helper_1_2(helper_fmuls, cpu_tmp32, - cpu_fpr[rs1], cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fmuls(cpu_tmp32, + cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0x4a: /* fmuld */ @@ -2444,8 +2480,8 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fmuld); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fmuld(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x4b: /* fmulq */ @@ -2454,23 +2490,23 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fmulq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fmulq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0x4d: /* fdivs */ gen_clear_float_exceptions(); - tcg_gen_helper_1_2(helper_fdivs, cpu_tmp32, - cpu_fpr[rs1], cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdivs(cpu_tmp32, + cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0x4e: gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fdivd); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdivd(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x4f: /* fdivq */ @@ -2478,16 +2514,15 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_QT0(QFPREG(rs1)); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fdivq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdivq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0x69: /* fsmuld */ CHECK_FPU_FEATURE(dc, FSMULD); gen_clear_float_exceptions(); - tcg_gen_helper_0_2(helper_fsmuld, cpu_fpr[rs1], - cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fsmuld(cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x6e: /* fdmulq */ @@ -2495,84 +2530,82 @@ static void disas_sparc_insn(DisasContext * dc) gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fdmulq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdmulq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0xc4: /* fitos */ gen_clear_float_exceptions(); - tcg_gen_helper_1_1(helper_fitos, cpu_tmp32, - cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fitos(cpu_tmp32, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0xc6: /* fdtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_1_0(helper_fdtos, cpu_tmp32); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdtos(cpu_tmp32); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0xc7: /* fqtos */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_1_0(helper_fqtos, cpu_tmp32); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fqtos(cpu_tmp32); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0xc8: /* fitod */ - tcg_gen_helper_0_1(helper_fitod, cpu_fpr[rs2]); + gen_helper_fitod(cpu_fpr[rs2]); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xc9: /* fstod */ - tcg_gen_helper_0_1(helper_fstod, cpu_fpr[rs2]); + gen_helper_fstod(cpu_fpr[rs2]); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xcb: /* fqtod */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fqtod); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fqtod(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xcc: /* fitoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - tcg_gen_helper_0_1(helper_fitoq, cpu_fpr[rs2]); + gen_helper_fitoq(cpu_fpr[rs2]); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0xcd: /* fstoq */ CHECK_FPU_FEATURE(dc, FLOAT128); - tcg_gen_helper_0_1(helper_fstoq, cpu_fpr[rs2]); + gen_helper_fstoq(cpu_fpr[rs2]); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0xce: /* fdtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fdtoq); + gen_helper_fdtoq(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0xd1: /* fstoi */ gen_clear_float_exceptions(); - tcg_gen_helper_1_1(helper_fstoi, cpu_tmp32, - cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fstoi(cpu_tmp32, cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0xd2: /* fdtoi */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_1_0(helper_fdtoi, cpu_tmp32); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdtoi(cpu_tmp32); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0xd3: /* fqtoi */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_1_0(helper_fqtoi, cpu_tmp32); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fqtoi(cpu_tmp32); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; #ifdef TARGET_SPARC64 @@ -2595,67 +2628,67 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x6: /* V9 fnegd */ gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnegd); + gen_helper_fnegd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x7: /* V9 fnegq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); - tcg_gen_helper_0_0(helper_fnegq); + gen_helper_fnegq(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0xa: /* V9 fabsd */ gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fabsd); + gen_helper_fabsd(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0xb: /* V9 fabsq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); - tcg_gen_helper_0_0(helper_fabsq); + gen_helper_fabsq(); gen_op_store_QT0_fpr(QFPREG(rd)); break; case 0x81: /* V9 fstox */ gen_clear_float_exceptions(); - tcg_gen_helper_0_1(helper_fstox, cpu_fpr[rs2]); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fstox(cpu_fpr[rs2]); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x82: /* V9 fdtox */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fdtox); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fdtox(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x83: /* V9 fqtox */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT1(QFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fqtox); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fqtox(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x84: /* V9 fxtos */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_1_0(helper_fxtos, cpu_tmp32); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fxtos(cpu_tmp32); + gen_helper_check_ieee_exceptions(); tcg_gen_mov_i32(cpu_fpr[rd], cpu_tmp32); break; case 0x88: /* V9 fxtod */ gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fxtod); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fxtod(); + gen_helper_check_ieee_exceptions(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x8c: /* V9 fxtoq */ CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_DT1(DFPREG(rs2)); gen_clear_float_exceptions(); - tcg_gen_helper_0_0(helper_fxtoq); - tcg_gen_helper_0_0(helper_check_ieee_exceptions); + gen_helper_fxtoq(); + gen_helper_check_ieee_exceptions(); gen_op_store_QT0_fpr(QFPREG(rd)); break; #endif @@ -2721,7 +2754,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -2736,7 +2769,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -2754,7 +2787,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_fcond(r_cond, fcc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -2819,7 +2852,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_cond(r_cond, icc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -2837,7 +2870,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_cond(r_cond, icc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -2852,7 +2885,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_cond(r_cond, icc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -2870,7 +2903,7 @@ static void disas_sparc_insn(DisasContext * dc) int l1; \ \ l1 = gen_new_label(); \ - r_cond = tcg_temp_new(TCG_TYPE_TL); \ + r_cond = tcg_temp_new(); \ cond = GET_FIELD_SP(insn, 14, 17); \ gen_cond(r_cond, icc, cond); \ tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, \ @@ -3139,15 +3172,13 @@ static void disas_sparc_insn(DisasContext * dc) #endif case 0xe: CHECK_IU_FEATURE(dc, DIV); - tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, - cpu_src2); + gen_helper_udiv(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) gen_op_div_cc(cpu_dst); break; case 0xf: CHECK_IU_FEATURE(dc, DIV); - tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, - cpu_src2); + gen_helper_sdiv(cpu_dst, cpu_src1, cpu_src2); if (xop & 0x10) gen_op_div_cc(cpu_dst); break; @@ -3231,7 +3262,7 @@ static void disas_sparc_insn(DisasContext * dc) #else case 0x2: /* V9 wrccr */ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_helper_0_1(helper_wrccr, cpu_dst); + gen_helper_wrccr(cpu_dst); break; case 0x3: /* V9 wrasi */ tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); @@ -3260,22 +3291,19 @@ static void disas_sparc_insn(DisasContext * dc) if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); - tcg_gen_helper_0_1(helper_set_softint, - cpu_tmp64); + gen_helper_set_softint(cpu_tmp64); break; case 0x15: /* Softint clear */ if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); - tcg_gen_helper_0_1(helper_clear_softint, - cpu_tmp64); + gen_helper_clear_softint(cpu_tmp64); break; case 0x16: /* Softint write */ if (!supervisor(dc)) goto illegal_insn; tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2); - tcg_gen_helper_0_1(helper_write_softint, - cpu_tmp64); + gen_helper_write_softint(cpu_tmp64); break; case 0x17: /* Tick compare */ #if !defined(CONFIG_USER_ONLY) @@ -3283,16 +3311,16 @@ static void disas_sparc_insn(DisasContext * dc) goto illegal_insn; #endif { - TCGv r_tickptr; + TCGv_ptr r_tickptr; tcg_gen_xor_tl(cpu_tick_cmpr, cpu_src1, cpu_src2); - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, tick)); - tcg_gen_helper_0_2(helper_tick_set_limit, - r_tickptr, cpu_tick_cmpr); - tcg_temp_free(r_tickptr); + gen_helper_tick_set_limit(r_tickptr, + cpu_tick_cmpr); + tcg_temp_free_ptr(r_tickptr); } break; case 0x18: /* System tick */ @@ -3301,16 +3329,16 @@ static void disas_sparc_insn(DisasContext * dc) goto illegal_insn; #endif { - TCGv r_tickptr; + TCGv_ptr r_tickptr; tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, stick)); - tcg_gen_helper_0_2(helper_tick_set_count, - r_tickptr, cpu_dst); - tcg_temp_free(r_tickptr); + gen_helper_tick_set_count(r_tickptr, + cpu_dst); + tcg_temp_free_ptr(r_tickptr); } break; case 0x19: /* System tick compare */ @@ -3319,16 +3347,16 @@ static void disas_sparc_insn(DisasContext * dc) goto illegal_insn; #endif { - TCGv r_tickptr; + TCGv_ptr r_tickptr; tcg_gen_xor_tl(cpu_stick_cmpr, cpu_src1, cpu_src2); - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, stick)); - tcg_gen_helper_0_2(helper_tick_set_limit, - r_tickptr, cpu_stick_cmpr); - tcg_temp_free(r_tickptr); + gen_helper_tick_set_limit(r_tickptr, + cpu_stick_cmpr); + tcg_temp_free_ptr(r_tickptr); } break; @@ -3350,10 +3378,10 @@ static void disas_sparc_insn(DisasContext * dc) #ifdef TARGET_SPARC64 switch (rd) { case 0: - tcg_gen_helper_0_0(helper_saved); + gen_helper_saved(); break; case 1: - tcg_gen_helper_0_0(helper_restored); + gen_helper_restored(); break; case 2: /* UA2005 allclean */ case 3: /* UA2005 otherw */ @@ -3365,7 +3393,7 @@ static void disas_sparc_insn(DisasContext * dc) } #else tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2); - tcg_gen_helper_0_1(helper_wrpsr, cpu_dst); + gen_helper_wrpsr(cpu_dst); save_state(dc, cpu_cond); gen_op_next_insn(); tcg_gen_exit_tb(0); @@ -3382,64 +3410,64 @@ static void disas_sparc_insn(DisasContext * dc) switch (rd) { case 0: // tpc { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tpc)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); } break; case 1: // tnpc { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tnpc)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); } break; case 2: // tstate { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_st_tl(cpu_tmp0, r_tsptr, offsetof(trap_state, tstate)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); } break; case 3: // tt { - TCGv r_tsptr; + TCGv_ptr r_tsptr; - r_tsptr = tcg_temp_new(TCG_TYPE_PTR); + r_tsptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tsptr, cpu_env, offsetof(CPUState, tsptr)); tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); tcg_gen_st_i32(cpu_tmp32, r_tsptr, offsetof(trap_state, tt)); - tcg_temp_free(r_tsptr); + tcg_temp_free_ptr(r_tsptr); } break; case 4: // tick { - TCGv r_tickptr; + TCGv_ptr r_tickptr; - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, tick)); - tcg_gen_helper_0_2(helper_tick_set_count, - r_tickptr, cpu_tmp0); - tcg_temp_free(r_tickptr); + gen_helper_tick_set_count(r_tickptr, + cpu_tmp0); + tcg_temp_free_ptr(r_tickptr); } break; case 5: // tba @@ -3447,7 +3475,7 @@ static void disas_sparc_insn(DisasContext * dc) break; case 6: // pstate save_state(dc, cpu_cond); - tcg_gen_helper_0_1(helper_wrpstate, cpu_tmp0); + gen_helper_wrpstate(cpu_tmp0); gen_op_next_insn(); tcg_gen_exit_tb(0); dc->is_br = 1; @@ -3464,7 +3492,7 @@ static void disas_sparc_insn(DisasContext * dc) psrpil)); break; case 9: // cwp - tcg_gen_helper_0_1(helper_wrcwp, cpu_tmp0); + gen_helper_wrcwp(cpu_tmp0); break; case 10: // cansave tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_tmp0); @@ -3550,15 +3578,15 @@ static void disas_sparc_insn(DisasContext * dc) break; case 31: // hstick_cmpr { - TCGv r_tickptr; + TCGv_ptr r_tickptr; tcg_gen_mov_tl(cpu_hstick_cmpr, cpu_tmp0); - r_tickptr = tcg_temp_new(TCG_TYPE_PTR); + r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUState, hstick)); - tcg_gen_helper_0_2(helper_tick_set_limit, - r_tickptr, cpu_hstick_cmpr); - tcg_temp_free(r_tickptr); + gen_helper_tick_set_limit(r_tickptr, + cpu_hstick_cmpr); + tcg_temp_free_ptr(r_tickptr); } break; case 6: // hver readonly @@ -3577,7 +3605,7 @@ static void disas_sparc_insn(DisasContext * dc) TCGv r_cond; int l1; - r_cond = tcg_temp_new(TCG_TYPE_TL); + r_cond = tcg_temp_new(); if (insn & (1 << 18)) { if (cc == 0) gen_cond(r_cond, 0, cond); @@ -3615,8 +3643,7 @@ static void disas_sparc_insn(DisasContext * dc) case 0x2e: /* V9 popc */ { cpu_src2 = get_src2(insn, cpu_src2); - tcg_gen_helper_1_1(helper_popc, cpu_dst, - cpu_src2); + gen_helper_popc(cpu_dst, cpu_src2); gen_movl_TN_reg(rd, cpu_dst); } case 0x2f: /* V9 movr */ @@ -3677,16 +3704,14 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, - cpu_src2); + gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); gen_movl_TN_reg(rd, cpu_dst); break; case 0x012: /* VIS I array16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, - cpu_src2); + gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); tcg_gen_shli_i64(cpu_dst, cpu_dst, 1); gen_movl_TN_reg(rd, cpu_dst); break; @@ -3694,8 +3719,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1, - cpu_src2); + gen_helper_array8(cpu_dst, cpu_src1, cpu_src2); tcg_gen_shli_i64(cpu_dst, cpu_dst, 2); gen_movl_TN_reg(rd, cpu_dst); break; @@ -3703,8 +3727,7 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); cpu_src1 = get_src1(insn, cpu_src1); gen_movl_reg_TN(rs2, cpu_src2); - tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1, - cpu_src2); + gen_helper_alignaddr(cpu_dst, cpu_src1, cpu_src2); gen_movl_TN_reg(rd, cpu_dst); break; case 0x019: /* VIS II bmask */ @@ -3715,105 +3738,105 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmple16); + gen_helper_fcmple16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x022: /* VIS I fcmpne16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmpne16); + gen_helper_fcmpne16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x024: /* VIS I fcmple32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmple32); + gen_helper_fcmple32(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x026: /* VIS I fcmpne32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmpne32); + gen_helper_fcmpne32(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x028: /* VIS I fcmpgt16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmpgt16); + gen_helper_fcmpgt16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x02a: /* VIS I fcmpeq16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmpeq16); + gen_helper_fcmpeq16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x02c: /* VIS I fcmpgt32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmpgt32); + gen_helper_fcmpgt32(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x02e: /* VIS I fcmpeq32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fcmpeq32); + gen_helper_fcmpeq32(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x031: /* VIS I fmul8x16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmul8x16); + gen_helper_fmul8x16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x033: /* VIS I fmul8x16au */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmul8x16au); + gen_helper_fmul8x16au(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x035: /* VIS I fmul8x16al */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmul8x16al); + gen_helper_fmul8x16al(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x036: /* VIS I fmul8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmul8sux16); + gen_helper_fmul8sux16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x037: /* VIS I fmul8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmul8ulx16); + gen_helper_fmul8ulx16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x038: /* VIS I fmuld8sux16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmuld8sux16); + gen_helper_fmuld8sux16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x039: /* VIS I fmuld8ulx16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fmuld8ulx16); + gen_helper_fmuld8ulx16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x03a: /* VIS I fpack32 */ @@ -3826,14 +3849,14 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_faligndata); + gen_helper_faligndata(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x04b: /* VIS I fpmerge */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fpmerge); + gen_helper_fpmerge(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x04c: /* VIS II bshuffle */ @@ -3843,56 +3866,56 @@ static void disas_sparc_insn(DisasContext * dc) CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fexpand); + gen_helper_fexpand(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x050: /* VIS I fpadd16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fpadd16); + gen_helper_fpadd16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x051: /* VIS I fpadd16s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_1_2(helper_fpadd16s, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_fpadd16s(cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x052: /* VIS I fpadd32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fpadd32); + gen_helper_fpadd32(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x053: /* VIS I fpadd32s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_1_2(helper_fpadd32s, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_fpadd32s(cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x054: /* VIS I fpsub16 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fpsub16); + gen_helper_fpsub16(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x055: /* VIS I fpsub16s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_1_2(helper_fpsub16s, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_fpsub16s(cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x056: /* VIS I fpsub32 */ CHECK_FPU_FEATURE(dc, VIS1); gen_op_load_fpr_DT0(DFPREG(rs1)); gen_op_load_fpr_DT1(DFPREG(rs2)); - tcg_gen_helper_0_0(helper_fpsub32); + gen_helper_fpsub32(); gen_op_store_DT0_fpr(DFPREG(rd)); break; case 0x057: /* VIS I fpsub32s */ CHECK_FPU_FEATURE(dc, VIS1); - tcg_gen_helper_1_2(helper_fpsub32s, cpu_fpr[rd], - cpu_fpr[rs1], cpu_fpr[rs2]); + gen_helper_fpsub32s(cpu_fpr[rd], + cpu_fpr[rs1], cpu_fpr[rs2]); break; case 0x060: /* VIS I fzero */ CHECK_FPU_FEATURE(dc, VIS1); @@ -4089,7 +4112,7 @@ static void disas_sparc_insn(DisasContext * dc) #endif #ifdef TARGET_SPARC64 } else if (xop == 0x39) { /* V9 return */ - TCGv r_const; + TCGv_i32 r_const; save_state(dc, cpu_cond); cpu_src1 = get_src1(insn, cpu_src1); @@ -4104,11 +4127,11 @@ static void disas_sparc_insn(DisasContext * dc) } else tcg_gen_mov_tl(cpu_dst, cpu_src1); } - tcg_gen_helper_0_0(helper_restore); + gen_helper_restore(); gen_mov_pc_npc(dc, cpu_cond); r_const = tcg_const_i32(3); - tcg_gen_helper_0_2(helper_check_align, cpu_dst, r_const); - tcg_temp_free(r_const); + gen_helper_check_align(cpu_dst, r_const); + tcg_temp_free_i32(r_const); tcg_gen_mov_tl(cpu_npc, cpu_dst); dc->npc = DYNAMIC_PC; goto jmp_insn; @@ -4129,16 +4152,16 @@ static void disas_sparc_insn(DisasContext * dc) switch (xop) { case 0x38: /* jmpl */ { - TCGv r_const; + TCGv r_pc; + TCGv_i32 r_const; - r_const = tcg_const_tl(dc->pc); - gen_movl_TN_reg(rd, r_const); - tcg_temp_free(r_const); + r_pc = tcg_const_tl(dc->pc); + gen_movl_TN_reg(rd, r_pc); + tcg_temp_free(r_pc); gen_mov_pc_npc(dc, cpu_cond); r_const = tcg_const_i32(3); - tcg_gen_helper_0_2(helper_check_align, cpu_dst, - r_const); - tcg_temp_free(r_const); + gen_helper_check_align(cpu_dst, r_const); + tcg_temp_free_i32(r_const); tcg_gen_mov_tl(cpu_npc, cpu_dst); dc->npc = DYNAMIC_PC; } @@ -4146,34 +4169,33 @@ static void disas_sparc_insn(DisasContext * dc) #if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64) case 0x39: /* rett, V9 return */ { - TCGv r_const; + TCGv_i32 r_const; if (!supervisor(dc)) goto priv_insn; gen_mov_pc_npc(dc, cpu_cond); r_const = tcg_const_i32(3); - tcg_gen_helper_0_2(helper_check_align, cpu_dst, - r_const); - tcg_temp_free(r_const); + gen_helper_check_align(cpu_dst, r_const); + tcg_temp_free_i32(r_const); tcg_gen_mov_tl(cpu_npc, cpu_dst); dc->npc = DYNAMIC_PC; - tcg_gen_helper_0_0(helper_rett); + gen_helper_rett(); } goto jmp_insn; #endif case 0x3b: /* flush */ if (!((dc)->def->features & CPU_FEATURE_FLUSH)) goto unimp_flush; - tcg_gen_helper_0_1(helper_flush, cpu_dst); + gen_helper_flush(cpu_dst); break; case 0x3c: /* save */ save_state(dc, cpu_cond); - tcg_gen_helper_0_0(helper_save); + gen_helper_save(); gen_movl_TN_reg(rd, cpu_dst); break; case 0x3d: /* restore */ save_state(dc, cpu_cond); - tcg_gen_helper_0_0(helper_restore); + gen_helper_restore(); gen_movl_TN_reg(rd, cpu_dst); break; #if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64) @@ -4185,14 +4207,14 @@ static void disas_sparc_insn(DisasContext * dc) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; - tcg_gen_helper_0_0(helper_done); + gen_helper_done(); goto jmp_insn; case 1: if (!supervisor(dc)) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; - tcg_gen_helper_0_0(helper_retry); + gen_helper_retry(); goto jmp_insn; default: goto illegal_insn; @@ -4247,13 +4269,12 @@ static void disas_sparc_insn(DisasContext * dc) if (rd & 1) goto illegal_insn; else { - TCGv r_const; + TCGv_i32 r_const; save_state(dc, cpu_cond); r_const = tcg_const_i32(7); - tcg_gen_helper_0_2(helper_check_align, cpu_addr, - r_const); // XXX remove - tcg_temp_free(r_const); + gen_helper_check_align(cpu_addr, r_const); // XXX remove + tcg_temp_free_i32(r_const); gen_address_mask(dc, cpu_addr); tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64); @@ -4443,33 +4464,33 @@ static void disas_sparc_insn(DisasContext * dc) gen_address_mask(dc, cpu_addr); if (rd == 1) { tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx); - tcg_gen_helper_0_1(helper_ldxfsr, cpu_tmp64); + gen_helper_ldxfsr(cpu_tmp64); } else #else { tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx); - tcg_gen_helper_0_1(helper_ldfsr, cpu_tmp32); + gen_helper_ldfsr(cpu_tmp32); } #endif break; case 0x22: /* load quad fpreg */ { - TCGv r_const; + TCGv_i32 r_const; CHECK_FPU_FEATURE(dc, FLOAT128); r_const = tcg_const_i32(dc->mem_idx); - tcg_gen_helper_0_2(helper_ldqf, cpu_addr, r_const); - tcg_temp_free(r_const); + gen_helper_ldqf(cpu_addr, r_const); + tcg_temp_free_i32(r_const); gen_op_store_QT0_fpr(QFPREG(rd)); } break; case 0x23: /* load double fpreg */ { - TCGv r_const; + TCGv_i32 r_const; r_const = tcg_const_i32(dc->mem_idx); - tcg_gen_helper_0_2(helper_lddf, cpu_addr, r_const); - tcg_temp_free(r_const); + gen_helper_lddf(cpu_addr, r_const); + tcg_temp_free_i32(r_const); gen_op_store_DT0_fpr(DFPREG(rd)); } break; @@ -4496,14 +4517,13 @@ static void disas_sparc_insn(DisasContext * dc) if (rd & 1) goto illegal_insn; else { - TCGv r_const; + TCGv_i32 r_const; save_state(dc, cpu_cond); gen_address_mask(dc, cpu_addr); r_const = tcg_const_i32(7); - tcg_gen_helper_0_2(helper_check_align, cpu_addr, - r_const); // XXX remove - tcg_temp_free(r_const); + gen_helper_check_align(cpu_addr, r_const); // XXX remove + tcg_temp_free_i32(r_const); gen_movl_reg_TN(rd + 1, cpu_tmp0); tcg_gen_concat_tl_i64(cpu_tmp64, cpu_tmp0, cpu_val); tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx); @@ -4595,13 +4615,13 @@ static void disas_sparc_insn(DisasContext * dc) #ifdef TARGET_SPARC64 /* V9 stqf, store quad fpreg */ { - TCGv r_const; + TCGv_i32 r_const; CHECK_FPU_FEATURE(dc, FLOAT128); gen_op_load_fpr_QT0(QFPREG(rd)); r_const = tcg_const_i32(dc->mem_idx); - tcg_gen_helper_0_2(helper_stqf, cpu_addr, r_const); - tcg_temp_free(r_const); + gen_helper_stqf(cpu_addr, r_const); + tcg_temp_free_i32(r_const); } break; #else /* !TARGET_SPARC64 */ @@ -4618,12 +4638,12 @@ static void disas_sparc_insn(DisasContext * dc) #endif case 0x27: /* store double fpreg */ { - TCGv r_const; + TCGv_i32 r_const; gen_op_load_fpr_DT0(DFPREG(rd)); r_const = tcg_const_i32(dc->mem_idx); - tcg_gen_helper_0_2(helper_stdf, cpu_addr, r_const); - tcg_temp_free(r_const); + gen_helper_stdf(cpu_addr, r_const); + tcg_temp_free_i32(r_const); } break; default: @@ -4638,13 +4658,12 @@ static void disas_sparc_insn(DisasContext * dc) break; case 0x36: /* V9 stqfa */ { - TCGv r_const; + TCGv_i32 r_const; CHECK_FPU_FEATURE(dc, FLOAT128); r_const = tcg_const_i32(7); - tcg_gen_helper_0_2(helper_check_align, cpu_addr, - r_const); - tcg_temp_free(r_const); + gen_helper_check_align(cpu_addr, r_const); + tcg_temp_free_i32(r_const); gen_op_load_fpr_QT0(QFPREG(rd)); gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); } @@ -4693,35 +4712,35 @@ static void disas_sparc_insn(DisasContext * dc) return; illegal_insn: { - TCGv r_const; + TCGv_i32 r_const; save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_ILL_INSN); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); dc->is_br = 1; } return; unimp_flush: { - TCGv r_const; + TCGv_i32 r_const; save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_UNIMP_FLUSH); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); dc->is_br = 1; } return; #if !defined(CONFIG_USER_ONLY) priv_insn: { - TCGv r_const; + TCGv_i32 r_const; save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_PRIV_INSN); - tcg_gen_helper_0_1(raise_exception, r_const); - tcg_temp_free(r_const); + gen_helper_raise_exception(r_const); + tcg_temp_free_i32(r_const); dc->is_br = 1; } return; @@ -4745,7 +4764,7 @@ static void disas_sparc_insn(DisasContext * dc) save_state(dc, cpu_cond); r_const = tcg_const_i32(TT_NCP_INSN); - tcg_gen_helper_0_1(raise_exception, r_const); + gen_helper_raise_exception(r_const); tcg_temp_free(r_const); dc->is_br = 1; } @@ -4780,15 +4799,15 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, #endif gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; - cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL); - cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32); - cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64); + cpu_tmp0 = tcg_temp_new(); + cpu_tmp32 = tcg_temp_new_i32(); + cpu_tmp64 = tcg_temp_new_i64(); - cpu_dst = tcg_temp_local_new(TCG_TYPE_TL); + cpu_dst = tcg_temp_local_new(); // loads and stores - cpu_val = tcg_temp_local_new(TCG_TYPE_TL); - cpu_addr = tcg_temp_local_new(TCG_TYPE_TL); + cpu_val = tcg_temp_local_new(); + cpu_addr = tcg_temp_local_new(); num_insns = 0; max_insns = tb->cflags & CF_COUNT_MASK; @@ -4801,7 +4820,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, if (env->breakpoints[j] == dc->pc) { if (dc->pc != pc_start) save_state(dc, cpu_cond); - tcg_gen_helper_0_0(helper_debug); + gen_helper_debug(); tcg_gen_exit_tb(0); dc->is_br = 1; goto exit_gen_loop; @@ -4852,8 +4871,8 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, tcg_temp_free(cpu_addr); tcg_temp_free(cpu_val); tcg_temp_free(cpu_dst); - tcg_temp_free(cpu_tmp64); - tcg_temp_free(cpu_tmp32); + tcg_temp_free_i64(cpu_tmp64); + tcg_temp_free_i32(cpu_tmp32); tcg_temp_free(cpu_tmp0); if (tb->cflags & CF_LAST_IO) gen_io_end(); @@ -4936,100 +4955,79 @@ void gen_intermediate_code_init(CPUSPARCState *env) if (!inited) { inited = 1; - cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); - cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0, - offsetof(CPUState, regwptr), - "regwptr"); + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + cpu_regwptr = tcg_global_mem_new_ptr(TCG_AREG0, + offsetof(CPUState, regwptr), + "regwptr"); #ifdef TARGET_SPARC64 - cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32, - TCG_AREG0, offsetof(CPUState, xcc), - "xcc"); - cpu_asi = tcg_global_mem_new(TCG_TYPE_I32, - TCG_AREG0, offsetof(CPUState, asi), - "asi"); - cpu_fprs = tcg_global_mem_new(TCG_TYPE_I32, - TCG_AREG0, offsetof(CPUState, fprs), - "fprs"); - cpu_gsr = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, gsr), + cpu_xcc = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, xcc), + "xcc"); + cpu_asi = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, asi), + "asi"); + cpu_fprs = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, fprs), + "fprs"); + cpu_gsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gsr), "gsr"); - cpu_tick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, + cpu_tick_cmpr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tick_cmpr), "tick_cmpr"); - cpu_stick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, + cpu_stick_cmpr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, stick_cmpr), "stick_cmpr"); - cpu_hstick_cmpr = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, + cpu_hstick_cmpr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hstick_cmpr), "hstick_cmpr"); - cpu_hintp = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, - offsetof(CPUState, hintp), + cpu_hintp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hintp), "hintp"); - cpu_htba = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, - offsetof(CPUState, htba), - "htba"); - cpu_hver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, - offsetof(CPUState, hver), - "hver"); - cpu_ssr = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, + cpu_htba = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, htba), + "htba"); + cpu_hver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, hver), + "hver"); + cpu_ssr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, ssr), "ssr"); - cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, + cpu_ver = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, version), "ver"); - cpu_softint = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, - offsetof(CPUState, softint), - "softint"); + cpu_softint = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, softint), + "softint"); #else - cpu_wim = tcg_global_mem_new(TCG_TYPE_I32, - TCG_AREG0, offsetof(CPUState, wim), + cpu_wim = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, wim), "wim"); #endif - cpu_cond = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, cond), + cpu_cond = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cond), "cond"); - cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, cc_src), + cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src), "cc_src"); - cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, + cpu_cc_src2 = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_src2), "cc_src2"); - cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, cc_dst), + cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, cc_dst), "cc_dst"); - cpu_psr = tcg_global_mem_new(TCG_TYPE_I32, - TCG_AREG0, offsetof(CPUState, psr), - "psr"); - cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, fsr), + cpu_psr = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUState, psr), + "psr"); + cpu_fsr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, fsr), "fsr"); - cpu_pc = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, pc), + cpu_pc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, pc), "pc"); - cpu_npc = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, npc), - "npc"); - cpu_y = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, y), "y"); + cpu_npc = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, npc), + "npc"); + cpu_y = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, y), "y"); #ifndef CONFIG_USER_ONLY - cpu_tbr = tcg_global_mem_new(TCG_TYPE_TL, - TCG_AREG0, offsetof(CPUState, tbr), + cpu_tbr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, tbr), "tbr"); #endif for (i = 1; i < 8; i++) - cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0, + cpu_gregs[i] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUState, gregs[i]), gregnames[i]); for (i = 0; i < TARGET_FPREGS; i++) - cpu_fpr[i] = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0, - offsetof(CPUState, fpr[i]), - fregnames[i]); + cpu_fpr[i] = tcg_global_mem_new_i32(TCG_AREG0, + offsetof(CPUState, fpr[i]), + fregnames[i]); /* register helpers */ -#undef DEF_HELPER -#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); +#define GEN_HELPER 2 #include "helper.h" } } |