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-rw-r--r--target-ppc/excp_helper.c19
-rw-r--r--target-ppc/fpu_helper.c26
-rw-r--r--target-ppc/kvm.c2
-rw-r--r--target-ppc/mmu-hash32.c24
-rw-r--r--target-ppc/mmu-hash64.c15
-rw-r--r--target-ppc/mmu_helper.c43
-rw-r--r--target-ppc/translate_init.c2
-rw-r--r--target-ppc/user_only_helper.c2
8 files changed, 75 insertions, 58 deletions
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index d541929743..a58655b5c7 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -43,13 +43,15 @@ void ppc_cpu_do_interrupt(CPUState *cs)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- env->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
void ppc_hw_interrupt(CPUPPCState *env)
{
- env->exception_index = POWERPC_EXCP_NONE;
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
}
#else /* defined(CONFIG_USER_ONLY) */
@@ -68,8 +70,8 @@ static inline void dump_syscall(CPUPPCState *env)
*/
static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
{
+ CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- CPUState *cs;
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
int lpes0, lpes1, lev;
@@ -135,7 +137,6 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
fprintf(stderr, "Machine check while not allowed. "
"Entering checkstop state\n");
}
- cs = CPU(cpu);
cs->halted = 1;
cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
@@ -204,7 +205,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
LOG_EXCP("Ignore floating point exception\n");
- env->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
return;
}
@@ -662,7 +663,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp)
hreg_compute_hflags(env);
env->nip = vector;
/* Reset exception state */
- env->exception_index = POWERPC_EXCP_NONE;
+ cs->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
if ((env->mmu_model == POWERPC_MMU_BOOKE) ||
@@ -679,7 +680,7 @@ void ppc_cpu_do_interrupt(CPUState *cs)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- powerpc_excp(cpu, env->excp_model, env->exception_index);
+ powerpc_excp(cpu, env->excp_model, cs->exception_index);
}
void ppc_hw_interrupt(CPUPPCState *env)
@@ -815,10 +816,12 @@ static void cpu_dump_rfi(target_ulong RA, target_ulong msr)
void helper_raise_exception_err(CPUPPCState *env, uint32_t exception,
uint32_t error_code)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
#if 0
printf("Raise exception %3x code : %d\n", exception, error_code);
#endif
- env->exception_index = exception;
+ cs->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit(env);
}
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index e7f329566d..fd91239d37 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -119,6 +119,7 @@ uint32_t helper_compute_fprf(CPUPPCState *env, uint64_t arg, uint32_t set_fprf)
static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
int set_fpcc)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
uint64_t ret = 0;
int ve;
@@ -155,7 +156,7 @@ static inline uint64_t fload_invalid_op_excp(CPUPPCState *env, int op,
}
/* We must update the target FPR before raising the exception */
if (ve != 0) {
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
@@ -224,6 +225,8 @@ static inline void float_zero_divide_excp(CPUPPCState *env)
static inline void float_overflow_excp(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
env->fpscr |= 1 << FPSCR_OX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
@@ -232,7 +235,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
} else {
env->fpscr |= 1 << FPSCR_XX;
@@ -242,6 +245,8 @@ static inline void float_overflow_excp(CPUPPCState *env)
static inline void float_underflow_excp(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
env->fpscr |= 1 << FPSCR_UX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
@@ -250,13 +255,15 @@ static inline void float_underflow_excp(CPUPPCState *env)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
}
}
static inline void float_inexact_excp(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
+
env->fpscr |= 1 << FPSCR_XX;
/* Update the floating-point exception summary */
env->fpscr |= 1 << FPSCR_FX;
@@ -264,7 +271,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We must update the target FPR before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
}
}
@@ -316,6 +323,7 @@ void helper_fpscr_clrbit(CPUPPCState *env, uint32_t bit)
void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
int prev;
prev = (env->fpscr >> bit) & 1;
@@ -439,7 +447,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
/* Update the floating-point enabled exception summary */
env->fpscr |= 1 << FPSCR_FEX;
/* We have to update Rc1 before raising the exception */
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
break;
}
}
@@ -447,6 +455,7 @@ void helper_fpscr_setbit(CPUPPCState *env, uint32_t bit)
void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
target_ulong prev, new;
int i;
@@ -468,7 +477,7 @@ void helper_store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
}
if ((fpscr_ex & fpscr_eex) != 0) {
env->fpscr |= 1 << FPSCR_FEX;
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
/* XXX: we should compute it properly */
env->error_code = POWERPC_EXCP_FP;
} else {
@@ -484,6 +493,7 @@ void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask)
void helper_float_check_status(CPUPPCState *env)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
int status = get_float_exception_flags(&env->fp_status);
if (status & float_flag_divbyzero) {
@@ -496,11 +506,11 @@ void helper_float_check_status(CPUPPCState *env)
float_inexact_excp(env);
}
- if (env->exception_index == POWERPC_EXCP_PROGRAM &&
+ if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
(env->error_code & POWERPC_EXCP_FP)) {
/* Differred floating-point exception after target FPR update */
if (msr_fe0 != 0 || msr_fe1 != 0) {
- helper_raise_exception_err(env, env->exception_index,
+ helper_raise_exception_err(env, cs->exception_index,
env->error_code);
}
}
diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 32e7a8c0a7..81ec959b23 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -1178,7 +1178,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu)
if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
cs->halted = 1;
- env->exception_index = EXCP_HLT;
+ cs->exception_index = EXCP_HLT;
}
return 0;
diff --git a/target-ppc/mmu-hash32.c b/target-ppc/mmu-hash32.c
index 6a77dc4f97..aa87084238 100644
--- a/target-ppc/mmu-hash32.c
+++ b/target-ppc/mmu-hash32.c
@@ -222,6 +222,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
target_ulong eaddr, int rwx,
hwaddr *raddr, int *prot)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
LOG_MMU("direct store...\n");
@@ -238,7 +239,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
if (rwx == 2) {
/* No code fetch is allowed in direct-store areas */
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
return 1;
}
@@ -249,7 +250,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
break;
case ACCESS_FLOAT:
/* Floating point load/store */
- env->exception_index = POWERPC_EXCP_ALIGN;
+ cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = POWERPC_EXCP_ALIGN_FP;
env->spr[SPR_DAR] = eaddr;
return 1;
@@ -272,7 +273,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
return 0;
case ACCESS_EXT:
/* eciwx or ecowx */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -290,7 +291,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
*raddr = eaddr;
return 0;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -383,6 +384,7 @@ static hwaddr ppc_hash32_pte_raddr(target_ulong sr, ppc_hash_pte32_t pte,
int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
int mmu_idx)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
target_ulong sr;
hwaddr pte_offset;
ppc_hash_pte32_t pte;
@@ -409,10 +411,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
if (raddr != -1) {
if (need_prot[rwx] & ~prot) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -449,7 +451,7 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
/* 5. Check for segment level no-execute violation */
if ((rwx == 2) && (sr & SR32_NX)) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
return 1;
}
@@ -458,10 +460,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
pte_offset = ppc_hash32_htab_lookup(env, sr, eaddr, &pte);
if (pte_offset == -1) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -483,10 +485,10 @@ int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr, int rwx,
/* Access right violation */
LOG_MMU("PTE access rejected\n");
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 438d0b732f..7186c0dbb4 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -457,6 +457,7 @@ static hwaddr ppc_hash64_pte_raddr(ppc_slb_t *slb, ppc_hash_pte64_t pte,
int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
int rwx, int mmu_idx)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
ppc_slb_t *slb;
hwaddr pte_offset;
ppc_hash_pte64_t pte;
@@ -483,10 +484,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
if (!slb) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISEG;
+ cs->exception_index = POWERPC_EXCP_ISEG;
env->error_code = 0;
} else {
- env->exception_index = POWERPC_EXCP_DSEG;
+ cs->exception_index = POWERPC_EXCP_DSEG;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
}
@@ -495,7 +496,7 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
/* 3. Check for segment level no-execute violation */
if ((rwx == 2) && (slb->vsid & SLB_VSID_N)) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
return 1;
}
@@ -504,10 +505,10 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
pte_offset = ppc_hash64_htab_lookup(env, slb, eaddr, &pte);
if (pte_offset == -1) {
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x40000000;
} else {
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (rwx == 1) {
@@ -530,12 +531,12 @@ int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong eaddr,
/* Access right violation */
LOG_MMU("PTE access rejected\n");
if (rwx == 2) {
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
} else {
target_ulong dsisr = 0;
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = eaddr;
if (need_prot[rwx] & ~pp_prot) {
diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c
index 8e2f8e736a..b6abd974e3 100644
--- a/target-ppc/mmu_helper.c
+++ b/target-ppc/mmu_helper.c
@@ -1491,6 +1491,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
int rw, int mmu_idx)
{
+ CPUState *cs = CPU(ppc_env_get_cpu(env));
mmu_ctx_t ctx;
int access_type;
int ret = 0;
@@ -1510,24 +1511,24 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
} else if (ret < 0) {
- LOG_MMU_STATE(CPU(ppc_env_get_cpu(env)));
+ LOG_MMU_STATE(cs);
if (access_type == ACCESS_CODE) {
switch (ret) {
case -1:
/* No matches in page tables or TLB */
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
- env->exception_index = POWERPC_EXCP_IFTLB;
+ cs->exception_index = POWERPC_EXCP_IFTLB;
env->error_code = 1 << 18;
env->spr[SPR_IMISS] = address;
env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
goto tlb_miss;
case POWERPC_MMU_SOFT_74xx:
- env->exception_index = POWERPC_EXCP_IFTLB;
+ cs->exception_index = POWERPC_EXCP_IFTLB;
goto tlb_miss_74xx;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
- env->exception_index = POWERPC_EXCP_ITLB;
+ cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = address;
env->spr[SPR_40x_ESR] = 0x00000000;
@@ -1536,7 +1537,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
booke206_update_mas_tlb_miss(env, address, rw);
/* fall through */
case POWERPC_MMU_BOOKE:
- env->exception_index = POWERPC_EXCP_ITLB;
+ cs->exception_index = POWERPC_EXCP_ITLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address;
return -1;
@@ -1555,7 +1556,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case -2:
/* Access rights violation */
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000;
break;
case -3:
@@ -1564,13 +1565,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
(env->mmu_model == POWERPC_MMU_BOOKE206)) {
env->spr[SPR_BOOKE_ESR] = 0x00000000;
}
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
break;
case -4:
/* Direct store exception */
/* No code fetch is allowed in direct-store areas */
- env->exception_index = POWERPC_EXCP_ISI;
+ cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x10000000;
break;
}
@@ -1581,10 +1582,10 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
if (rw == 1) {
- env->exception_index = POWERPC_EXCP_DSTLB;
+ cs->exception_index = POWERPC_EXCP_DSTLB;
env->error_code = 1 << 16;
} else {
- env->exception_index = POWERPC_EXCP_DLTLB;
+ cs->exception_index = POWERPC_EXCP_DLTLB;
env->error_code = 0;
}
env->spr[SPR_DMISS] = address;
@@ -1598,9 +1599,9 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case POWERPC_MMU_SOFT_74xx:
if (rw == 1) {
- env->exception_index = POWERPC_EXCP_DSTLB;
+ cs->exception_index = POWERPC_EXCP_DSTLB;
} else {
- env->exception_index = POWERPC_EXCP_DLTLB;
+ cs->exception_index = POWERPC_EXCP_DLTLB;
}
tlb_miss_74xx:
/* Implement LRU algorithm */
@@ -1611,7 +1612,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case POWERPC_MMU_SOFT_4xx:
case POWERPC_MMU_SOFT_4xx_Z:
- env->exception_index = POWERPC_EXCP_DTLB;
+ cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_40x_DEAR] = address;
if (rw) {
@@ -1628,7 +1629,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
booke206_update_mas_tlb_miss(env, address, rw);
/* fall through */
case POWERPC_MMU_BOOKE:
- env->exception_index = POWERPC_EXCP_DTLB;
+ cs->exception_index = POWERPC_EXCP_DTLB;
env->error_code = 0;
env->spr[SPR_BOOKE_DEAR] = address;
env->spr[SPR_BOOKE_ESR] = rw ? ESR_ST : 0;
@@ -1644,7 +1645,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case -2:
/* Access rights violation */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
if (env->mmu_model == POWERPC_MMU_SOFT_4xx
|| env->mmu_model == POWERPC_MMU_SOFT_4xx_Z) {
@@ -1670,13 +1671,13 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
switch (access_type) {
case ACCESS_FLOAT:
/* Floating point load/store */
- env->exception_index = POWERPC_EXCP_ALIGN;
+ cs->exception_index = POWERPC_EXCP_ALIGN;
env->error_code = POWERPC_EXCP_ALIGN_FP;
env->spr[SPR_DAR] = address;
break;
case ACCESS_RES:
/* lwarx, ldarx or stwcx. */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = address;
if (rw == 1) {
@@ -1687,7 +1688,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
case ACCESS_EXT:
/* eciwx or ecowx */
- env->exception_index = POWERPC_EXCP_DSI;
+ cs->exception_index = POWERPC_EXCP_DSI;
env->error_code = 0;
env->spr[SPR_DAR] = address;
if (rw == 1) {
@@ -1698,7 +1699,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
break;
default:
printf("DSI: invalid exception (%d)\n", ret);
- env->exception_index = POWERPC_EXCP_PROGRAM;
+ cs->exception_index = POWERPC_EXCP_PROGRAM;
env->error_code =
POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL;
env->spr[SPR_DAR] = address;
@@ -1709,7 +1710,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, target_ulong address,
}
#if 0
printf("%s: set exception to %d %02x\n", __func__,
- env->exception, env->error_code);
+ cs->exception, env->error_code);
#endif
ret = 1;
}
@@ -2909,6 +2910,6 @@ void tlb_fill(CPUPPCState *env, target_ulong addr, int is_write, int mmu_idx,
/* now we have a real cpu fault */
cpu_restore_state(env, retaddr);
}
- helper_raise_exception_err(env, env->exception_index, env->error_code);
+ helper_raise_exception_err(env, cpu->exception_index, env->error_code);
}
}
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 703b3d8797..e22d82f604 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8422,7 +8422,7 @@ static void ppc_cpu_reset(CPUState *s)
env->reserve_addr = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */
env->pending_interrupts = 0;
- env->exception_index = POWERPC_EXCP_NONE;
+ s->exception_index = POWERPC_EXCP_NONE;
env->error_code = 0;
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
diff --git a/target-ppc/user_only_helper.c b/target-ppc/user_only_helper.c
index a7c99e032b..829f66f504 100644
--- a/target-ppc/user_only_helper.c
+++ b/target-ppc/user_only_helper.c
@@ -39,7 +39,7 @@ int ppc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
env->spr[SPR_DAR] = address;
env->spr[SPR_DSISR] = error_code;
}
- env->exception_index = exception;
+ cs->exception_index = exception;
env->error_code = error_code;
return 1;
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-11 14:56:41 +0000