diff options
Diffstat (limited to 'target-alpha')
| -rw-r--r-- | target-alpha/cpu.h | 5 | ||||
| -rw-r--r-- | target-alpha/exec.h | 12 |
2 files changed, 16 insertions, 1 deletions
diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index f5d90c7936..a1f92abcdc 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -315,6 +315,11 @@ enum { EXCP_STQ_C, }; +/* Alpha-specific interrupt pending bits. */ +#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0 +#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1 +#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2 + /* Hardware interrupt (entInt) constants. */ enum { INT_K_IP, diff --git a/target-alpha/exec.h b/target-alpha/exec.h index 6ae96d148b..7a325e7a75 100644 --- a/target-alpha/exec.h +++ b/target-alpha/exec.h @@ -39,7 +39,17 @@ register struct CPUAlphaState *env asm(AREG0); static inline int cpu_has_work(CPUState *env) { - return (env->interrupt_request & CPU_INTERRUPT_HARD); + /* Here we are checking to see if the CPU should wake up from HALT. + We will have gotten into this state only for WTINT from PALmode. */ + /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU + asleep even if (some) interrupts have been asserted. For now, + assume that if a CPU really wants to stay asleep, it will mask + interrupts at the chipset level, which will prevent these bits + from being set in the first place. */ + return env->interrupt_request & (CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb) |