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-rw-r--r--hw/avr/arduino.c20
-rw-r--r--hw/mips/gt64xxx_pci.c59
-rw-r--r--hw/mips/trace-events6
-rw-r--r--hw/misc/led.c1
-rw-r--r--hw/tricore/Kconfig8
-rw-r--r--hw/tricore/meson.build2
-rw-r--r--hw/tricore/tc27x_soc.c246
-rw-r--r--hw/tricore/triboard.c98
8 files changed, 410 insertions, 30 deletions
diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c
index 3c8388490d..3ff31492fa 100644
--- a/hw/avr/arduino.c
+++ b/hw/avr/arduino.c
@@ -75,7 +75,10 @@ static void arduino_duemilanove_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
- /* https://www.arduino.cc/en/Main/ArduinoBoardDuemilanove */
+ /*
+ * https://www.arduino.cc/en/Main/ArduinoBoardDuemilanove
+ * https://www.arduino.cc/en/uploads/Main/arduino-duemilanove-schematic.pdf
+ */
mc->desc = "Arduino Duemilanove (ATmega168)",
mc->alias = "2009";
amc->mcu_type = TYPE_ATMEGA168_MCU;
@@ -87,7 +90,10 @@ static void arduino_uno_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
- /* https://store.arduino.cc/arduino-uno-rev3 */
+ /*
+ * https://store.arduino.cc/arduino-uno-rev3
+ * https://www.arduino.cc/en/uploads/Main/arduino-uno-schematic.pdf
+ */
mc->desc = "Arduino UNO (ATmega328P)";
mc->alias = "uno";
amc->mcu_type = TYPE_ATMEGA328_MCU;
@@ -99,7 +105,10 @@ static void arduino_mega_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
- /* https://www.arduino.cc/en/Main/ArduinoBoardMega */
+ /*
+ * https://www.arduino.cc/en/Main/ArduinoBoardMega
+ * https://www.arduino.cc/en/uploads/Main/arduino-mega2560-schematic.pdf
+ */
mc->desc = "Arduino Mega (ATmega1280)";
mc->alias = "mega";
amc->mcu_type = TYPE_ATMEGA1280_MCU;
@@ -111,7 +120,10 @@ static void arduino_mega2560_class_init(ObjectClass *oc, void *data)
MachineClass *mc = MACHINE_CLASS(oc);
ArduinoMachineClass *amc = ARDUINO_MACHINE_CLASS(oc);
- /* https://store.arduino.cc/arduino-mega-2560-rev3 */
+ /*
+ * https://store.arduino.cc/arduino-mega-2560-rev3
+ * https://www.arduino.cc/en/uploads/Main/arduino-mega2560_R3-sch.pdf
+ */
mc->desc = "Arduino Mega 2560 (ATmega2560)";
mc->alias = "mega2560";
amc->mcu_type = TYPE_ATMEGA2560_MCU;
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 588e6f9930..43349d6837 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -385,13 +385,13 @@ static void gt64120_writel(void *opaque, hwaddr addr,
{
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
- uint32_t saddr;
+ uint32_t saddr = addr >> 2;
+ trace_gt64120_write(addr, val);
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
- saddr = (addr & 0xfff) >> 2;
switch (saddr) {
/* CPU Configuration */
@@ -464,7 +464,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -474,7 +474,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -516,7 +516,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented device register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -529,7 +529,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Read-only registers, do nothing */
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Read-only register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -566,7 +566,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented DMA register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -579,7 +579,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* Not implemented */
qemu_log_mask(LOG_UNIMP,
"gt64120: Unimplemented timer register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
@@ -622,8 +622,8 @@ static void gt64120_writel(void *opaque, hwaddr addr,
case GT_PCI1_CFGDATA:
/* not implemented */
qemu_log_mask(LOG_UNIMP,
- "gt64120: Unimplemented timer register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "gt64120: Unimplemented PCI register write "
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
case GT_PCI0_CFGADDR:
@@ -643,19 +643,19 @@ static void gt64120_writel(void *opaque, hwaddr addr,
/* not really implemented */
s->regs[saddr] = ~(~(s->regs[saddr]) | ~(val & 0xfffffffe));
s->regs[saddr] |= !!(s->regs[saddr] & 0xfffffffe);
- trace_gt64120_write("INTRCAUSE", size, val);
+ trace_gt64120_write_intreg("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
s->regs[saddr] = val & 0x3c3ffffe;
- trace_gt64120_write("INTRMASK", size, val);
+ trace_gt64120_write_intreg("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
s->regs[saddr] = val & 0x03fffffe;
- trace_gt64120_write("ICMASK", size, val);
+ trace_gt64120_write_intreg("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
s->regs[saddr] = val & 0x0000003f;
- trace_gt64120_write("SERR0MASK", size, val);
+ trace_gt64120_write_intreg("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@@ -683,7 +683,7 @@ static void gt64120_writel(void *opaque, hwaddr addr,
default:
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register write "
- "reg:0x03%x size:%u value:0x%0*" PRIx64 "\n",
+ "reg:0x%03x size:%u value:0x%0*" PRIx64 "\n",
saddr << 2, size, size << 1, val);
break;
}
@@ -695,9 +695,8 @@ static uint64_t gt64120_readl(void *opaque,
GT64120State *s = opaque;
PCIHostState *phb = PCI_HOST_BRIDGE(s);
uint32_t val;
- uint32_t saddr;
+ uint32_t saddr = addr >> 2;
- saddr = (addr & 0xfff) >> 2;
switch (saddr) {
/* CPU Configuration */
@@ -931,19 +930,19 @@ static uint64_t gt64120_readl(void *opaque,
/* Interrupts */
case GT_INTRCAUSE:
val = s->regs[saddr];
- trace_gt64120_read("INTRCAUSE", size, val);
+ trace_gt64120_read_intreg("INTRCAUSE", size, val);
break;
case GT_INTRMASK:
val = s->regs[saddr];
- trace_gt64120_read("INTRMASK", size, val);
+ trace_gt64120_read_intreg("INTRMASK", size, val);
break;
case GT_PCI0_ICMASK:
val = s->regs[saddr];
- trace_gt64120_read("ICMASK", size, val);
+ trace_gt64120_read_intreg("ICMASK", size, val);
break;
case GT_PCI0_SERR0MASK:
val = s->regs[saddr];
- trace_gt64120_read("SERR0MASK", size, val);
+ trace_gt64120_read_intreg("SERR0MASK", size, val);
break;
/* Reserved when only PCI_0 is configured. */
@@ -960,7 +959,7 @@ static uint64_t gt64120_readl(void *opaque,
val = s->regs[saddr];
qemu_log_mask(LOG_GUEST_ERROR,
"gt64120: Illegal register read "
- "reg:0x03%x size:%u value:0x%0*x\n",
+ "reg:0x%03x size:%u value:0x%0*x\n",
saddr << 2, size, size << 1, val);
break;
}
@@ -968,6 +967,7 @@ static uint64_t gt64120_readl(void *opaque,
if (!(s->regs[GT_CPU] & 0x00001000)) {
val = bswap32(val);
}
+ trace_gt64120_read(addr, val);
return val;
}
@@ -976,6 +976,10 @@ static const MemoryRegionOps isd_mem_ops = {
.read = gt64120_readl,
.write = gt64120_writel,
.endianness = DEVICE_NATIVE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
};
static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
@@ -1196,6 +1200,14 @@ static void gt64120_reset(DeviceState *dev)
gt64120_pci_mapping(s);
}
+static void gt64120_realize(DeviceState *dev, Error **errp)
+{
+ GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
+
+ memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
+ "gt64120-isd", 0x1000);
+}
+
PCIBus *gt64120_register(qemu_irq *pic)
{
GT64120State *d;
@@ -1214,8 +1226,6 @@ PCIBus *gt64120_register(qemu_irq *pic)
get_system_io(),
PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- memory_region_init_io(&d->ISD_mem, OBJECT(dev), &isd_mem_ops, d,
- "isd-mem", 0x1000);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
return phb->bus;
@@ -1270,6 +1280,7 @@ static void gt64120_class_init(ObjectClass *klass, void *data)
DeviceClass *dc = DEVICE_CLASS(klass);
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
+ dc->realize = gt64120_realize;
dc->reset = gt64120_reset;
dc->vmsd = &vmstate_gt64120;
}
diff --git a/hw/mips/trace-events b/hw/mips/trace-events
index 915139d981..13ee731a48 100644
--- a/hw/mips/trace-events
+++ b/hw/mips/trace-events
@@ -1,4 +1,6 @@
# gt64xxx_pci.c
-gt64120_read(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
-gt64120_write(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
+gt64120_read(uint64_t addr, uint64_t value) "gt64120 read 0x%03"PRIx64" value:0x%08" PRIx64
+gt64120_write(uint64_t addr, uint64_t value) "gt64120 write 0x%03"PRIx64" value:0x%08" PRIx64
+gt64120_read_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 read %s size:%u value:0x%08" PRIx64
+gt64120_write_intreg(const char *regname, unsigned size, uint64_t value) "gt64120 write %s size:%u value:0x%08" PRIx64
gt64120_isd_remap(uint64_t from_length, uint64_t from_addr, uint64_t to_length, uint64_t to_addr) "ISD: 0x%08" PRIx64 "@0x%08" PRIx64 " -> 0x%08" PRIx64 "@0x%08" PRIx64
diff --git a/hw/misc/led.c b/hw/misc/led.c
index 5266d026d0..f552b8b648 100644
--- a/hw/misc/led.c
+++ b/hw/misc/led.c
@@ -20,6 +20,7 @@ static const char * const led_color_name[] = {
[LED_COLOR_BLUE] = "blue",
[LED_COLOR_CYAN] = "cyan",
[LED_COLOR_GREEN] = "green",
+ [LED_COLOR_YELLOW] = "yellow",
[LED_COLOR_AMBER] = "amber",
[LED_COLOR_ORANGE] = "orange",
[LED_COLOR_RED] = "red",
diff --git a/hw/tricore/Kconfig b/hw/tricore/Kconfig
index 9313409309..506e6183c1 100644
--- a/hw/tricore/Kconfig
+++ b/hw/tricore/Kconfig
@@ -1,2 +1,10 @@
config TRICORE
bool
+
+config TRIBOARD
+ bool
+ select TRICORE
+ select TC27X_SOC
+
+config TC27X_SOC
+ bool
diff --git a/hw/tricore/meson.build b/hw/tricore/meson.build
index 579aa13c78..77ff6fd137 100644
--- a/hw/tricore/meson.build
+++ b/hw/tricore/meson.build
@@ -1,4 +1,6 @@
tricore_ss = ss.source_set()
tricore_ss.add(when: 'CONFIG_TRICORE', if_true: files('tricore_testboard.c'))
+tricore_ss.add(when: 'CONFIG_TRIBOARD', if_true: files('triboard.c'))
+tricore_ss.add(when: 'CONFIG_TC27X_SOC', if_true: files('tc27x_soc.c'))
hw_arch += {'tricore': tricore_ss}
diff --git a/hw/tricore/tc27x_soc.c b/hw/tricore/tc27x_soc.c
new file mode 100644
index 0000000000..8af079e6b2
--- /dev/null
+++ b/hw/tricore/tc27x_soc.c
@@ -0,0 +1,246 @@
+/*
+ * Infineon tc27x SoC System emulation.
+ *
+ * Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
+ * Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/sysbus.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "qemu/units.h"
+#include "hw/misc/unimp.h"
+#include "exec/address-spaces.h"
+#include "qemu/log.h"
+#include "cpu.h"
+
+#include "hw/tricore/tc27x_soc.h"
+#include "hw/tricore/triboard.h"
+
+const MemmapEntry tc27x_soc_memmap[] = {
+ [TC27XD_DSPR2] = { 0x50000000, 120 * KiB },
+ [TC27XD_DCACHE2] = { 0x5001E000, 8 * KiB },
+ [TC27XD_DTAG2] = { 0x500C0000, 0xC00 },
+ [TC27XD_PSPR2] = { 0x50100000, 32 * KiB },
+ [TC27XD_PCACHE2] = { 0x50108000, 16 * KiB },
+ [TC27XD_PTAG2] = { 0x501C0000, 0x1800 },
+ [TC27XD_DSPR1] = { 0x60000000, 120 * KiB },
+ [TC27XD_DCACHE1] = { 0x6001E000, 8 * KiB },
+ [TC27XD_DTAG1] = { 0x600C0000, 0xC00 },
+ [TC27XD_PSPR1] = { 0x60100000, 32 * KiB },
+ [TC27XD_PCACHE1] = { 0x60108000, 16 * KiB },
+ [TC27XD_PTAG1] = { 0x601C0000, 0x1800 },
+ [TC27XD_DSPR0] = { 0x70000000, 112 * KiB },
+ [TC27XD_PSPR0] = { 0x70100000, 24 * KiB },
+ [TC27XD_PCACHE0] = { 0x70106000, 8 * KiB },
+ [TC27XD_PTAG0] = { 0x701C0000, 0xC00 },
+ [TC27XD_PFLASH0_C] = { 0x80000000, 2 * MiB },
+ [TC27XD_PFLASH1_C] = { 0x80200000, 2 * MiB },
+ [TC27XD_OLDA_C] = { 0x8FE70000, 32 * KiB },
+ [TC27XD_BROM_C] = { 0x8FFF8000, 32 * KiB },
+ [TC27XD_LMURAM_C] = { 0x90000000, 32 * KiB },
+ [TC27XD_EMEM_C] = { 0x9F000000, 1 * MiB },
+ [TC27XD_PFLASH0_U] = { 0xA0000000, 0x0 },
+ [TC27XD_PFLASH1_U] = { 0xA0200000, 0x0 },
+ [TC27XD_DFLASH0] = { 0xAF000000, 1 * MiB + 16 * KiB },
+ [TC27XD_DFLASH1] = { 0xAF110000, 64 * KiB },
+ [TC27XD_OLDA_U] = { 0xAFE70000, 0x0 },
+ [TC27XD_BROM_U] = { 0xAFFF8000, 0x0 },
+ [TC27XD_LMURAM_U] = { 0xB0000000, 0x0 },
+ [TC27XD_EMEM_U] = { 0xBF000000, 0x0 },
+ [TC27XD_PSPRX] = { 0xC0000000, 0x0 },
+ [TC27XD_DSPRX] = { 0xD0000000, 0x0 },
+};
+
+/*
+ * Initialize the auxiliary ROM region @mr and map it into
+ * the memory map at @base.
+ */
+static void make_rom(MemoryRegion *mr, const char *name,
+ hwaddr base, hwaddr size)
+{
+ memory_region_init_rom(mr, NULL, name, size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), base, mr);
+}
+
+/*
+ * Initialize the auxiliary RAM region @mr and map it into
+ * the memory map at @base.
+ */
+static void make_ram(MemoryRegion *mr, const char *name,
+ hwaddr base, hwaddr size)
+{
+ memory_region_init_ram(mr, NULL, name, size, &error_fatal);
+ memory_region_add_subregion(get_system_memory(), base, mr);
+}
+
+/*
+ * Create an alias of an entire original MemoryRegion @orig
+ * located at @base in the memory map.
+ */
+static void make_alias(MemoryRegion *mr, const char *name,
+ MemoryRegion *orig, hwaddr base)
+{
+ memory_region_init_alias(mr, NULL, name, orig, 0,
+ memory_region_size(orig));
+ memory_region_add_subregion(get_system_memory(), base, mr);
+}
+
+static void tc27x_soc_init_memory_mapping(DeviceState *dev_soc)
+{
+ TC27XSoCState *s = TC27X_SOC(dev_soc);
+ TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
+
+ make_ram(&s->cpu0mem.dspr, "CPU0.DSPR",
+ sc->memmap[TC27XD_DSPR0].base, sc->memmap[TC27XD_DSPR0].size);
+ make_ram(&s->cpu0mem.pspr, "CPU0.PSPR",
+ sc->memmap[TC27XD_PSPR0].base, sc->memmap[TC27XD_PSPR0].size);
+ make_ram(&s->cpu1mem.dspr, "CPU1.DSPR",
+ sc->memmap[TC27XD_DSPR1].base, sc->memmap[TC27XD_DSPR1].size);
+ make_ram(&s->cpu1mem.pspr, "CPU1.PSPR",
+ sc->memmap[TC27XD_PSPR1].base, sc->memmap[TC27XD_PSPR1].size);
+ make_ram(&s->cpu2mem.dspr, "CPU2.DSPR",
+ sc->memmap[TC27XD_DSPR2].base, sc->memmap[TC27XD_DSPR2].size);
+ make_ram(&s->cpu2mem.pspr, "CPU2.PSPR",
+ sc->memmap[TC27XD_PSPR2].base, sc->memmap[TC27XD_PSPR2].size);
+
+ /* TODO: Control Cache mapping with Memory Test Unit (MTU) */
+ make_ram(&s->cpu2mem.dcache, "CPU2.DCACHE",
+ sc->memmap[TC27XD_DCACHE2].base, sc->memmap[TC27XD_DCACHE2].size);
+ make_ram(&s->cpu2mem.dtag, "CPU2.DTAG",
+ sc->memmap[TC27XD_DTAG2].base, sc->memmap[TC27XD_DTAG2].size);
+ make_ram(&s->cpu2mem.pcache, "CPU2.PCACHE",
+ sc->memmap[TC27XD_PCACHE2].base, sc->memmap[TC27XD_PCACHE2].size);
+ make_ram(&s->cpu2mem.ptag, "CPU2.PTAG",
+ sc->memmap[TC27XD_PTAG2].base, sc->memmap[TC27XD_PTAG2].size);
+
+ make_ram(&s->cpu1mem.dcache, "CPU1.DCACHE",
+ sc->memmap[TC27XD_DCACHE1].base, sc->memmap[TC27XD_DCACHE1].size);
+ make_ram(&s->cpu1mem.dtag, "CPU1.DTAG",
+ sc->memmap[TC27XD_DTAG1].base, sc->memmap[TC27XD_DTAG1].size);
+ make_ram(&s->cpu1mem.pcache, "CPU1.PCACHE",
+ sc->memmap[TC27XD_PCACHE1].base, sc->memmap[TC27XD_PCACHE1].size);
+ make_ram(&s->cpu1mem.ptag, "CPU1.PTAG",
+ sc->memmap[TC27XD_PTAG1].base, sc->memmap[TC27XD_PTAG1].size);
+
+ make_ram(&s->cpu0mem.pcache, "CPU0.PCACHE",
+ sc->memmap[TC27XD_PCACHE0].base, sc->memmap[TC27XD_PCACHE0].size);
+ make_ram(&s->cpu0mem.ptag, "CPU0.PTAG",
+ sc->memmap[TC27XD_PTAG0].base, sc->memmap[TC27XD_PTAG0].size);
+
+ /*
+ * TriCore QEMU executes CPU0 only, thus it is sufficient to map
+ * LOCAL.PSPR/LOCAL.DSPR exclusively onto PSPR0/DSPR0.
+ */
+ make_alias(&s->psprX, "LOCAL.PSPR", &s->cpu0mem.pspr,
+ sc->memmap[TC27XD_PSPRX].base);
+ make_alias(&s->dsprX, "LOCAL.DSPR", &s->cpu0mem.dspr,
+ sc->memmap[TC27XD_DSPRX].base);
+
+ make_ram(&s->flashmem.pflash0_c, "PF0",
+ sc->memmap[TC27XD_PFLASH0_C].base, sc->memmap[TC27XD_PFLASH0_C].size);
+ make_ram(&s->flashmem.pflash1_c, "PF1",
+ sc->memmap[TC27XD_PFLASH1_C].base, sc->memmap[TC27XD_PFLASH1_C].size);
+ make_ram(&s->flashmem.dflash0, "DF0",
+ sc->memmap[TC27XD_DFLASH0].base, sc->memmap[TC27XD_DFLASH0].size);
+ make_ram(&s->flashmem.dflash1, "DF1",
+ sc->memmap[TC27XD_DFLASH1].base, sc->memmap[TC27XD_DFLASH1].size);
+ make_ram(&s->flashmem.olda_c, "OLDA",
+ sc->memmap[TC27XD_OLDA_C].base, sc->memmap[TC27XD_OLDA_C].size);
+ make_rom(&s->flashmem.brom_c, "BROM",
+ sc->memmap[TC27XD_BROM_C].base, sc->memmap[TC27XD_BROM_C].size);
+ make_ram(&s->flashmem.lmuram_c, "LMURAM",
+ sc->memmap[TC27XD_LMURAM_C].base, sc->memmap[TC27XD_LMURAM_C].size);
+ make_ram(&s->flashmem.emem_c, "EMEM",
+ sc->memmap[TC27XD_EMEM_C].base, sc->memmap[TC27XD_EMEM_C].size);
+
+ make_alias(&s->flashmem.pflash0_u, "PF0.U", &s->flashmem.pflash0_c,
+ sc->memmap[TC27XD_PFLASH0_U].base);
+ make_alias(&s->flashmem.pflash1_u, "PF1.U", &s->flashmem.pflash1_c,
+ sc->memmap[TC27XD_PFLASH1_U].base);
+ make_alias(&s->flashmem.olda_u, "OLDA.U", &s->flashmem.olda_c,
+ sc->memmap[TC27XD_OLDA_U].base);
+ make_alias(&s->flashmem.brom_u, "BROM.U", &s->flashmem.brom_c,
+ sc->memmap[TC27XD_BROM_U].base);
+ make_alias(&s->flashmem.lmuram_u, "LMURAM.U", &s->flashmem.lmuram_c,
+ sc->memmap[TC27XD_LMURAM_U].base);
+ make_alias(&s->flashmem.emem_u, "EMEM.U", &s->flashmem.emem_c,
+ sc->memmap[TC27XD_EMEM_U].base);
+}
+
+static void tc27x_soc_realize(DeviceState *dev_soc, Error **errp)
+{
+ TC27XSoCState *s = TC27X_SOC(dev_soc);
+ Error *err = NULL;
+
+ qdev_realize(DEVICE(&s->cpu), NULL, &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+
+ tc27x_soc_init_memory_mapping(dev_soc);
+}
+
+static void tc27x_soc_init(Object *obj)
+{
+ TC27XSoCState *s = TC27X_SOC(obj);
+ TC27XSoCClass *sc = TC27X_SOC_GET_CLASS(s);
+
+ object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type);
+}
+
+static Property tc27x_soc_properties[] = {
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void tc27x_soc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->realize = tc27x_soc_realize;
+ device_class_set_props(dc, tc27x_soc_properties);
+}
+
+static void tc277d_soc_class_init(ObjectClass *oc, void *data)
+{
+ TC27XSoCClass *sc = TC27X_SOC_CLASS(oc);
+
+ sc->name = "tc277d-soc";
+ sc->cpu_type = TRICORE_CPU_TYPE_NAME("tc27x");
+ sc->memmap = tc27x_soc_memmap;
+ sc->num_cpus = 1;
+}
+
+static const TypeInfo tc27x_soc_types[] = {
+ {
+ .name = "tc277d-soc",
+ .parent = TYPE_TC27X_SOC,
+ .class_init = tc277d_soc_class_init,
+ }, {
+ .name = TYPE_TC27X_SOC,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(TC27XSoCState),
+ .instance_init = tc27x_soc_init,
+ .class_size = sizeof(TC27XSoCClass),
+ .class_init = tc27x_soc_class_init,
+ .abstract = true,
+ },
+};
+
+DEFINE_TYPES(tc27x_soc_types)
diff --git a/hw/tricore/triboard.c b/hw/tricore/triboard.c
new file mode 100644
index 0000000000..16e2fd7e27
--- /dev/null
+++ b/hw/tricore/triboard.c
@@ -0,0 +1,98 @@
+/*
+ * Infineon TriBoard System emulation.
+ *
+ * Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
+ * Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "cpu.h"
+#include "net/net.h"
+#include "hw/boards.h"
+#include "hw/loader.h"
+#include "exec/address-spaces.h"
+#include "elf.h"
+#include "hw/tricore/tricore.h"
+#include "qemu/error-report.h"
+
+#include "hw/tricore/triboard.h"
+#include "hw/tricore/tc27x_soc.h"
+
+static void tricore_load_kernel(const char *kernel_filename)
+{
+ uint64_t entry;
+ long kernel_size;
+ TriCoreCPU *cpu;
+ CPUTriCoreState *env;
+
+ kernel_size = load_elf(kernel_filename, NULL,
+ NULL, NULL, &entry, NULL,
+ NULL, NULL, 0,
+ EM_TRICORE, 1, 0);
+ if (kernel_size <= 0) {
+ error_report("no kernel file '%s'", kernel_filename);
+ exit(1);
+ }
+ cpu = TRICORE_CPU(first_cpu);
+ env = &cpu->env;
+ env->PC = entry;
+}
+
+
+static void triboard_machine_init(MachineState *machine)
+{
+ TriBoardMachineState *ms = TRIBOARD_MACHINE(machine);
+ TriBoardMachineClass *amc = TRIBOARD_MACHINE_GET_CLASS(machine);
+
+ object_initialize_child(OBJECT(machine), "soc", &ms->tc27x_soc,
+ amc->soc_name);
+ sysbus_realize(SYS_BUS_DEVICE(&ms->tc27x_soc), &error_fatal);
+
+ if (machine->kernel_filename) {
+ tricore_load_kernel(machine->kernel_filename);
+ }
+}
+
+static void triboard_machine_tc277d_class_init(ObjectClass *oc,
+ void *data)
+{
+ MachineClass *mc = MACHINE_CLASS(oc);
+ TriBoardMachineClass *amc = TRIBOARD_MACHINE_CLASS(oc);
+
+ mc->init = triboard_machine_init;
+ mc->desc = "Infineon AURIX TriBoard TC277 (D-Step)";
+ mc->max_cpus = 1;
+ amc->soc_name = "tc277d-soc";
+};
+
+static const TypeInfo triboard_machine_types[] = {
+ {
+ .name = MACHINE_TYPE_NAME("KIT_AURIX_TC277_TRB"),
+ .parent = TYPE_TRIBOARD_MACHINE,
+ .class_init = triboard_machine_tc277d_class_init,
+ }, {
+ .name = TYPE_TRIBOARD_MACHINE,
+ .parent = TYPE_MACHINE,
+ .instance_size = sizeof(TriBoardMachineState),
+ .class_size = sizeof(TriBoardMachineClass),
+ .abstract = true,
+ },
+};
+
+DEFINE_TYPES(triboard_machine_types)
generated by cgit v1.2.3 (git 2.26.2) at 2025-02-27 21:51:20 +0000