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-rw-r--r--hw/riscv/sifive_u.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e75ca38783..87bbd10b21 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -602,10 +602,10 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* reset vector */
- uint32_t reset_vec[11] = {
+ uint32_t reset_vec[12] = {
s->msel, /* MSEL pin state */
0x00000297, /* 1: auipc t0, %pcrel_hi(fw_dyn) */
- 0x02828613, /* addi a2, t0, %pcrel_lo(1b) */
+ 0x02c28613, /* addi a2, t0, %pcrel_lo(1b) */
0xf1402573, /* csrr a0, mhartid */
0,
0,
@@ -614,6 +614,7 @@ static void sifive_u_machine_init(MachineState *machine)
start_addr_hi32,
fdt_load_addr, /* fdt_laddr: .dword */
0x00000000,
+ 0x00000000,
/* fw_dyn: */
};
if (riscv_is_32bit(&s->soc.u_cpus)) {