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-rw-r--r--hw/ppc/e500-ccsr.h6
-rw-r--r--hw/ppc/e500.h11
-rw-r--r--hw/ppc/mac.h11
-rw-r--r--hw/ppc/mpc8544_guts.c3
-rw-r--r--hw/ppc/ppc440_pcix.c6
-rw-r--r--hw/ppc/ppc440_uc.c6
-rw-r--r--hw/ppc/ppc4xx_pci.c3
-rw-r--r--hw/ppc/ppce500_spin.c6
-rw-r--r--hw/ppc/prep_systemio.c6
-rw-r--r--hw/ppc/rs6000_mc.c6
-rw-r--r--hw/ppc/spapr_rng.c3
11 files changed, 44 insertions, 23 deletions
diff --git a/hw/ppc/e500-ccsr.h b/hw/ppc/e500-ccsr.h
index 12a2ba4b97..f7fd73fc0d 100644
--- a/hw/ppc/e500-ccsr.h
+++ b/hw/ppc/e500-ccsr.h
@@ -2,14 +2,16 @@
#define E500_CCSR_H
#include "hw/sysbus.h"
+#include "qom/object.h"
-typedef struct PPCE500CCSRState {
+struct PPCE500CCSRState {
/*< private >*/
SysBusDevice parent;
/*< public >*/
MemoryRegion ccsr_space;
-} PPCE500CCSRState;
+};
+typedef struct PPCE500CCSRState PPCE500CCSRState;
#define TYPE_CCSR "e500-ccsr"
#define CCSR(obj) OBJECT_CHECK(PPCE500CCSRState, (obj), TYPE_CCSR)
diff --git a/hw/ppc/e500.h b/hw/ppc/e500.h
index 3fd9f825ca..5773460d5e 100644
--- a/hw/ppc/e500.h
+++ b/hw/ppc/e500.h
@@ -3,8 +3,9 @@
#include "hw/boards.h"
#include "hw/platform-bus.h"
+#include "qom/object.h"
-typedef struct PPCE500MachineState {
+struct PPCE500MachineState {
/*< private >*/
MachineState parent_obj;
@@ -12,9 +13,10 @@ typedef struct PPCE500MachineState {
* board supports dynamic sysbus devices
*/
PlatformBusDevice *pbus_dev;
-} PPCE500MachineState;
+};
+typedef struct PPCE500MachineState PPCE500MachineState;
-typedef struct PPCE500MachineClass {
+struct PPCE500MachineClass {
/*< private >*/
MachineClass parent_class;
@@ -36,7 +38,8 @@ typedef struct PPCE500MachineClass {
hwaddr pci_mmio_base;
hwaddr pci_mmio_bus_base;
hwaddr spin_base;
-} PPCE500MachineClass;
+};
+typedef struct PPCE500MachineClass PPCE500MachineClass;
void ppce500_init(MachineState *machine);
diff --git a/hw/ppc/mac.h b/hw/ppc/mac.h
index 6af87d1fa0..f4ef3f32b0 100644
--- a/hw/ppc/mac.h
+++ b/hw/ppc/mac.h
@@ -34,6 +34,7 @@
#include "hw/misc/mos6522.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/uninorth.h"
+#include "qom/object.h"
/* SMP is not enabled, for now */
#define MAX_CPUS 1
@@ -71,6 +72,7 @@
/* Core99 machine */
#define TYPE_CORE99_MACHINE MACHINE_TYPE_NAME("mac99")
+typedef struct Core99MachineState Core99MachineState;
#define CORE99_MACHINE(obj) OBJECT_CHECK(Core99MachineState, (obj), \
TYPE_CORE99_MACHINE)
@@ -78,22 +80,23 @@
#define CORE99_VIA_CONFIG_PMU 0x1
#define CORE99_VIA_CONFIG_PMU_ADB 0x2
-typedef struct Core99MachineState {
+struct Core99MachineState {
/*< private >*/
MachineState parent;
uint8_t via_config;
-} Core99MachineState;
+};
/* Grackle PCI */
#define TYPE_GRACKLE_PCI_HOST_BRIDGE "grackle-pcihost"
/* Mac NVRAM */
#define TYPE_MACIO_NVRAM "macio-nvram"
+typedef struct MacIONVRAMState MacIONVRAMState;
#define MACIO_NVRAM(obj) \
OBJECT_CHECK(MacIONVRAMState, (obj), TYPE_MACIO_NVRAM)
-typedef struct MacIONVRAMState {
+struct MacIONVRAMState {
/*< private >*/
SysBusDevice parent_obj;
/*< public >*/
@@ -103,7 +106,7 @@ typedef struct MacIONVRAMState {
MemoryRegion mem;
uint8_t *data;
-} MacIONVRAMState;
+};
void pmac_format_nvram_partition (MacIONVRAMState *nvr, int len);
#endif /* PPC_MAC_H */
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c
index b96ea36f98..f74bcdca16 100644
--- a/hw/ppc/mpc8544_guts.c
+++ b/hw/ppc/mpc8544_guts.c
@@ -22,6 +22,7 @@
#include "sysemu/runstate.h"
#include "cpu.h"
#include "hw/sysbus.h"
+#include "qom/object.h"
#define MPC8544_GUTS_MMIO_SIZE 0x1000
#define MPC8544_GUTS_RSTCR_RESET 0x02
@@ -54,6 +55,7 @@
#define MPC8544_GUTS_ADDR_SRDS2CR3 0xF18
#define TYPE_MPC8544_GUTS "mpc8544-guts"
+typedef struct GutsState GutsState;
#define MPC8544_GUTS(obj) OBJECT_CHECK(GutsState, (obj), TYPE_MPC8544_GUTS)
struct GutsState {
@@ -64,7 +66,6 @@ struct GutsState {
MemoryRegion iomem;
};
-typedef struct GutsState GutsState;
static uint64_t mpc8544_guts_read(void *opaque, hwaddr addr,
unsigned size)
diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c
index 2ee2d4f4fc..f82d520d25 100644
--- a/hw/ppc/ppc440_pcix.c
+++ b/hw/ppc/ppc440_pcix.c
@@ -30,6 +30,7 @@
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"
#include "trace.h"
+#include "qom/object.h"
struct PLBOutMap {
uint64_t la;
@@ -45,13 +46,14 @@ struct PLBInMap {
};
#define TYPE_PPC440_PCIX_HOST_BRIDGE "ppc440-pcix-host"
+typedef struct PPC440PCIXState PPC440PCIXState;
#define PPC440_PCIX_HOST_BRIDGE(obj) \
OBJECT_CHECK(PPC440PCIXState, (obj), TYPE_PPC440_PCIX_HOST_BRIDGE)
#define PPC440_PCIX_NR_POMS 3
#define PPC440_PCIX_NR_PIMS 3
-typedef struct PPC440PCIXState {
+struct PPC440PCIXState {
PCIHostState parent_obj;
PCIDevice *dev;
@@ -65,7 +67,7 @@ typedef struct PPC440PCIXState {
MemoryRegion container;
MemoryRegion iomem;
MemoryRegion busmem;
-} PPC440PCIXState;
+};
#define PPC440_REG_BASE 0x80000
#define PPC440_REG_SIZE 0xff
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c
index 38fc392438..73cb93a3a5 100644
--- a/hw/ppc/ppc440_uc.c
+++ b/hw/ppc/ppc440_uc.c
@@ -24,6 +24,7 @@
#include "sysemu/block-backend.h"
#include "sysemu/reset.h"
#include "ppc440.h"
+#include "qom/object.h"
/*****************************************************************************/
/* L2 Cache as SRAM */
@@ -1032,10 +1033,11 @@ void ppc4xx_dma_init(CPUPPCState *env, int dcr_base)
#include "hw/pci/pcie_host.h"
#define TYPE_PPC460EX_PCIE_HOST "ppc460ex-pcie-host"
+typedef struct PPC460EXPCIEState PPC460EXPCIEState;
#define PPC460EX_PCIE_HOST(obj) \
OBJECT_CHECK(PPC460EXPCIEState, (obj), TYPE_PPC460EX_PCIE_HOST)
-typedef struct PPC460EXPCIEState {
+struct PPC460EXPCIEState {
PCIExpressHost host;
MemoryRegion iomem;
@@ -1056,7 +1058,7 @@ typedef struct PPC460EXPCIEState {
uint32_t reg_mask;
uint32_t special;
uint32_t cfg;
-} PPC460EXPCIEState;
+};
#define DCRN_PCIE0_BASE 0x100
#define DCRN_PCIE1_BASE 0x120
diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c
index 503ef46b39..6ee7eeed98 100644
--- a/hw/ppc/ppc4xx_pci.c
+++ b/hw/ppc/ppc4xx_pci.c
@@ -30,6 +30,7 @@
#include "hw/pci/pci_host.h"
#include "exec/address-spaces.h"
#include "trace.h"
+#include "qom/object.h"
struct PCIMasterMap {
uint32_t la;
@@ -43,6 +44,7 @@ struct PCITargetMap {
uint32_t la;
};
+typedef struct PPC4xxPCIState PPC4xxPCIState;
#define PPC4xx_PCI_HOST_BRIDGE(obj) \
OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE)
@@ -59,7 +61,6 @@ struct PPC4xxPCIState {
MemoryRegion container;
MemoryRegion iomem;
};
-typedef struct PPC4xxPCIState PPC4xxPCIState;
#define PCIC0_CFGADDR 0x0
#define PCIC0_CFGDATA 0x4
diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c
index 66c1065db2..b1b6d559c4 100644
--- a/hw/ppc/ppce500_spin.c
+++ b/hw/ppc/ppce500_spin.c
@@ -34,6 +34,7 @@
#include "hw/sysbus.h"
#include "sysemu/hw_accel.h"
#include "e500.h"
+#include "qom/object.h"
#define MAX_CPUS 32
@@ -46,14 +47,15 @@ typedef struct spin_info {
} QEMU_PACKED SpinInfo;
#define TYPE_E500_SPIN "e500-spin"
+typedef struct SpinState SpinState;
#define E500_SPIN(obj) OBJECT_CHECK(SpinState, (obj), TYPE_E500_SPIN)
-typedef struct SpinState {
+struct SpinState {
SysBusDevice parent_obj;
MemoryRegion iomem;
SpinInfo spin[MAX_CPUS];
-} SpinState;
+};
static void spin_reset(DeviceState *dev)
{
diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c
index bbc51b6e9a..d13044acce 100644
--- a/hw/ppc/prep_systemio.c
+++ b/hw/ppc/prep_systemio.c
@@ -28,6 +28,7 @@
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
#include "exec/address-spaces.h"
+#include "qom/object.h"
#include "qemu/error-report.h" /* for error_report() */
#include "qemu/module.h"
#include "sysemu/runstate.h"
@@ -35,13 +36,14 @@
#include "trace.h"
#define TYPE_PREP_SYSTEMIO "prep-systemio"
+typedef struct PrepSystemIoState PrepSystemIoState;
#define PREP_SYSTEMIO(obj) \
OBJECT_CHECK(PrepSystemIoState, (obj), TYPE_PREP_SYSTEMIO)
/* Bit as defined in PowerPC Reference Plaform v1.1, sect. 6.1.5, p. 132 */
#define PREP_BIT(n) (1 << (7 - (n)))
-typedef struct PrepSystemIoState {
+struct PrepSystemIoState {
ISADevice parent_obj;
MemoryRegion ppc_parity_mem;
@@ -53,7 +55,7 @@ typedef struct PrepSystemIoState {
uint8_t ibm_planar_id; /* 0x0852 */
qemu_irq softreset_irq;
PortioList portio;
-} PrepSystemIoState;
+};
/* PORT 0092 -- Special Port 92 (Read/Write) */
diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c
index ce97365f5e..ec25a701dc 100644
--- a/hw/ppc/rs6000_mc.c
+++ b/hw/ppc/rs6000_mc.c
@@ -26,12 +26,14 @@
#include "hw/boards.h"
#include "qapi/error.h"
#include "trace.h"
+#include "qom/object.h"
#define TYPE_RS6000MC "rs6000-mc"
+typedef struct RS6000MCState RS6000MCState;
#define RS6000MC_DEVICE(obj) \
OBJECT_CHECK(RS6000MCState, (obj), TYPE_RS6000MC)
-typedef struct RS6000MCState {
+struct RS6000MCState {
ISADevice parent_obj;
/* see US patent 5,684,979 for details (expired 2001-11-04) */
uint32_t ram_size;
@@ -41,7 +43,7 @@ typedef struct RS6000MCState {
uint32_t end_address[8];
uint8_t port0820_index;
PortioList portio;
-} RS6000MCState;
+};
/* P0RT 0803 -- SIMM ID Register (32/8 MB) (Read Only) */
diff --git a/hw/ppc/spapr_rng.c b/hw/ppc/spapr_rng.c
index 85bf64d68e..b400438394 100644
--- a/hw/ppc/spapr_rng.c
+++ b/hw/ppc/spapr_rng.c
@@ -28,7 +28,9 @@
#include "hw/ppc/spapr.h"
#include "hw/qdev-properties.h"
#include "kvm_ppc.h"
+#include "qom/object.h"
+typedef struct SpaprRngState SpaprRngState;
#define SPAPR_RNG(obj) \
OBJECT_CHECK(SpaprRngState, (obj), TYPE_SPAPR_RNG)
@@ -38,7 +40,6 @@ struct SpaprRngState {
RngBackend *backend;
bool use_kvm;
};
-typedef struct SpaprRngState SpaprRngState;
struct HRandomData {
QemuSemaphore sem;
generated by cgit v1.2.3 (git 2.26.2) at 2024-12-01 22:48:38 +0000