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-rw-r--r--cpu-defs.h29
-rw-r--r--target-arm/cpu.h17
-rw-r--r--target-i386/cpu.h21
-rw-r--r--target-mips/cpu.h20
-rw-r--r--target-ppc/cpu.h22
-rw-r--r--target-sparc/cpu.h20
6 files changed, 38 insertions, 91 deletions
diff --git a/cpu-defs.h b/cpu-defs.h
index 912133ee6c..fb4f8e8a29 100644
--- a/cpu-defs.h
+++ b/cpu-defs.h
@@ -77,6 +77,9 @@ typedef unsigned long ram_addr_t;
#define MAX_BREAKPOINTS 32
+#define TB_JMP_CACHE_BITS 12
+#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
+
#define CPU_TLB_SIZE 256
typedef struct CPUTLBEntry {
@@ -91,4 +94,30 @@ typedef struct CPUTLBEntry {
target_phys_addr_t addend;
} CPUTLBEntry;
+#define CPU_COMMON \
+ struct TranslationBlock *current_tb; /* currently executing TB */ \
+ /* soft mmu support */ \
+ /* in order to avoid passing too many arguments to the memory \
+ write helpers, we store some rarely used information in the CPU \
+ context) */ \
+ unsigned long mem_write_pc; /* host pc at which the memory was \
+ written */ \
+ target_ulong mem_write_vaddr; /* target virtual addr at which the \
+ memory was written */ \
+ /* 0 = kernel, 1 = user */ \
+ CPUTLBEntry tlb_read[2][CPU_TLB_SIZE]; \
+ CPUTLBEntry tlb_write[2][CPU_TLB_SIZE]; \
+ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
+ \
+ /* from this point: preserved by CPU reset */ \
+ /* ice debug support */ \
+ target_ulong breakpoints[MAX_BREAKPOINTS]; \
+ int nb_breakpoints; \
+ int singlestep_enabled; \
+ \
+ /* user data */ \
+ void *opaque;
+
+
+
#endif
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ef7469d0c3..fc49b5a994 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -60,22 +60,9 @@ typedef struct CPUARMState {
jmp_buf jmp_env;
int exception_index;
int interrupt_request;
- struct TranslationBlock *current_tb;
int user_mode_only;
uint32_t address;
- /* ICE debug support. */
- target_ulong breakpoints[MAX_BREAKPOINTS];
- int nb_breakpoints;
- int singlestep_enabled;
-
- /* in order to avoid passing too many arguments to the memory
- write helpers, we store some rarely used information in the CPU
- context) */
- unsigned long mem_write_pc; /* host pc at which the memory was
- written */
- unsigned long mem_write_vaddr; /* target virtual addr at which the
- memory was written */
/* VFP coprocessor state. */
struct {
float64 regs[16];
@@ -93,8 +80,8 @@ typedef struct CPUARMState {
float_status fp_status;
} vfp;
- /* user data */
- void *opaque;
+ CPU_COMMON
+
} CPUARMState;
CPUARMState *cpu_arm_init(void);
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index f8373a1025..cd12ca17ed 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -497,28 +497,11 @@ typedef struct CPUX86State {
int error_code;
int exception_is_int;
target_ulong exception_next_eip;
- struct TranslationBlock *current_tb; /* currently executing TB */
target_ulong dr[8]; /* debug registers */
int interrupt_request;
int user_mode_only; /* user mode only simulation */
- /* soft mmu support */
- /* in order to avoid passing too many arguments to the memory
- write helpers, we store some rarely used information in the CPU
- context) */
- unsigned long mem_write_pc; /* host pc at which the memory was
- written */
- target_ulong mem_write_vaddr; /* target virtual addr at which the
- memory was written */
- /* 0 = kernel, 1 = user */
- CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
- CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
-
- /* from this point: preserved by CPU reset */
- /* ice debug support */
- target_ulong breakpoints[MAX_BREAKPOINTS];
- int nb_breakpoints;
- int singlestep_enabled;
+ CPU_COMMON
/* processor features (e.g. for CPUID insn) */
uint32_t cpuid_level;
@@ -538,8 +521,6 @@ typedef struct CPUX86State {
/* in order to simplify APIC support, we leave this pointer to the
user */
struct APICState *apic_state;
- /* user data */
- void *opaque;
} CPUX86State;
CPUX86State *cpu_x86_init(void);
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 8ed09d584d..3314c9d91b 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -162,24 +162,8 @@ struct CPUMIPSState {
#define MIPS_HFLAG_BR 0x0800 /* branch to register (can't link TB) */
target_ulong btarget; /* Jump / branch target */
int bcond; /* Branch condition (if needed) */
- struct TranslationBlock *current_tb; /* currently executing TB */
- /* soft mmu support */
- /* in order to avoid passing too many arguments to the memory
- write helpers, we store some rarely used information in the CPU
- context) */
- target_ulong mem_write_pc; /* host pc at which the memory was
- written */
- unsigned long mem_write_vaddr; /* target virtual addr at which the
- memory was written */
- /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
- CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
- CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
- /* ice debug support */
- target_ulong breakpoints[MAX_BREAKPOINTS];
- int nb_breakpoints;
- int singlestep_enabled; /* XXX: should use CPU single step mode instead */
- /* user data */
- void *opaque;
+
+ CPU_COMMON
};
#include "cpu-all.h"
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 8dd9cc12dd..fa7f524e9d 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -493,19 +493,10 @@ struct CPUPPCState {
/* floating point status and control register */
uint8_t fpscr[8];
- /* soft mmu support */
- /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
- CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
- CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
+ CPU_COMMON
+
int access_type; /* when a memory exception occurs, the access
type is stored here */
- /* in order to avoid passing too many arguments to the memory
- write helpers, we store some rarely used information in the CPU
- context) */
- unsigned long mem_write_pc; /* host pc at which the memory was
- written */
- unsigned long mem_write_vaddr; /* target virtual addr at which the
- memory was written */
/* MMU context */
/* Address space register */
@@ -564,22 +555,13 @@ struct CPUPPCState {
/* Those resources are used only in Qemu core */
jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
- struct TranslationBlock *current_tb; /* currently executing TB */
uint32_t hflags;
- /* ice debug support */
- target_ulong breakpoints[MAX_BREAKPOINTS];
- int nb_breakpoints;
- int singlestep_enabled; /* XXX: should use CPU single step mode instead */
-
/* Power management */
int power_mode;
/* temporary hack to handle OSI calls (only used if non NULL) */
int (*osi_call)(struct CPUPPCState *env);
-
- /* user data */
- void *opaque;
};
/*****************************************************************************/
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 999d5d7e68..baff0c4602 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -166,21 +166,11 @@ typedef struct CPUSPARCState {
int exception_index;
int interrupt_index;
int interrupt_request;
- struct TranslationBlock *current_tb;
- void *opaque;
/* NOTE: we allow 8 more registers to handle wrapping */
target_ulong regbase[NWINDOWS * 16 + 8];
- /* in order to avoid passing too many arguments to the memory
- write helpers, we store some rarely used information in the CPU
- context) */
- unsigned long mem_write_pc; /* host pc at which the memory was
- written */
- target_ulong mem_write_vaddr; /* target virtual addr at which the
- memory was written */
- /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
- CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
- CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
+ CPU_COMMON
+
/* MMU regs */
#if defined(TARGET_SPARC64)
uint64_t lsu;
@@ -222,12 +212,6 @@ typedef struct CPUSPARCState {
#if !defined(TARGET_SPARC64) && !defined(reg_T2)
target_ulong t2;
#endif
-
- /* ice debug support */
- target_ulong breakpoints[MAX_BREAKPOINTS];
- int nb_breakpoints;
- int singlestep_enabled; /* XXX: should use CPU single step mode instead */
-
} CPUSPARCState;
#if defined(TARGET_SPARC64)
#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
generated by cgit v1.2.3 (git 2.26.2) at 2024-11-23 09:14:32 +0000