diff options
| -rw-r--r-- | Makefile.target | 1 | ||||
| -rw-r--r-- | target-lm32/cpu-qom.h | 71 | ||||
| -rw-r--r-- | target-lm32/cpu.c | 60 | ||||
| -rw-r--r-- | target-lm32/cpu.h | 1 | ||||
| -rw-r--r-- | target-lm32/helper.c | 4 |
5 files changed, 136 insertions, 1 deletions
diff --git a/Makefile.target b/Makefile.target index 1110796e48..e88b896e38 100644 --- a/Makefile.target +++ b/Makefile.target @@ -93,6 +93,7 @@ libobj-$(TARGET_SPARC64) += vis_helper.o libobj-$(CONFIG_NEED_MMU) += mmu.o libobj-$(TARGET_ARM) += neon_helper.o iwmmxt_helper.o libobj-$(TARGET_ARM) += cpu.o +libobj-$(TARGET_LM32) += cpu.o libobj-$(TARGET_S390X) += cpu.o ifeq ($(TARGET_BASE_ARCH), sparc) libobj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h new file mode 100644 index 0000000000..4ae2eddafb --- /dev/null +++ b/target-lm32/cpu-qom.h @@ -0,0 +1,71 @@ +/* + * QEMU LatticeMico32 CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ +#ifndef QEMU_LM32_CPU_QOM_H +#define QEMU_LM32_CPU_QOM_H + +#include "qemu/cpu.h" +#include "cpu.h" + +#define TYPE_LM32_CPU "lm32-cpu" + +#define LM32_CPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(LM32CPUClass, (klass), TYPE_LM32_CPU) +#define LM32_CPU(obj) \ + OBJECT_CHECK(LM32CPU, (obj), TYPE_LM32_CPU) +#define LM32_CPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(LM32CPUClass, (obj), TYPE_LM32_CPU) + +/** + * LM32CPUClass: + * @parent_reset: The parent class' reset handler. + * + * A LatticeMico32 CPU model. + */ +typedef struct LM32CPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + void (*parent_reset)(CPUState *cpu); +} LM32CPUClass; + +/** + * LM32CPU: + * @env: #CPULM32State + * + * A LatticeMico32 CPU. + */ +typedef struct LM32CPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPULM32State env; +} LM32CPU; + +static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) +{ + return LM32_CPU(container_of(env, LM32CPU, env)); +} + +#define ENV_GET_CPU(e) CPU(lm32_env_get_cpu(e)) + + +#endif diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c new file mode 100644 index 0000000000..4ce7e3bf4c --- /dev/null +++ b/target-lm32/cpu.c @@ -0,0 +1,60 @@ +/* + * QEMU LatticeMico32 CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ + +#include "cpu-qom.h" +#include "qemu-common.h" + + +/* CPUClass::reset() */ +static void lm32_cpu_reset(CPUState *s) +{ + LM32CPU *cpu = LM32_CPU(s); + LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu); + CPULM32State *env = &cpu->env; + + lcc->parent_reset(s); + + cpu_state_reset(env); +} + +static void lm32_cpu_class_init(ObjectClass *oc, void *data) +{ + LM32CPUClass *lcc = LM32_CPU_CLASS(oc); + CPUClass *cc = CPU_CLASS(oc); + + lcc->parent_reset = cc->reset; + cc->reset = lm32_cpu_reset; +} + +static const TypeInfo lm32_cpu_type_info = { + .name = TYPE_LM32_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(LM32CPU), + .abstract = false, + .class_size = sizeof(LM32CPUClass), + .class_init = lm32_cpu_class_init, +}; + +static void lm32_cpu_register_types(void) +{ + type_register_static(&lm32_cpu_type_info); +} + +type_init(lm32_cpu_register_types) diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index a7d95464b8..422a55b063 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -184,6 +184,7 @@ struct CPULM32State { }; +#include "cpu-qom.h" CPULM32State *cpu_lm32_init(const char *cpu_model); void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf); diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 78076e4603..3cf86d7b76 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -194,6 +194,7 @@ static uint32_t cfg_by_def(const LM32Def *def) CPULM32State *cpu_lm32_init(const char *cpu_model) { + LM32CPU *cpu; CPULM32State *env; const LM32Def *def; static int tcg_initialized; @@ -203,7 +204,8 @@ CPULM32State *cpu_lm32_init(const char *cpu_model) return NULL; } - env = g_malloc0(sizeof(CPULM32State)); + cpu = LM32_CPU(object_new(TYPE_LM32_CPU)); + env = &cpu->env; env->features = def->features; env->num_bps = def->num_breakpoints; |