diff options
| -rw-r--r-- | hw/collie.c | 4 | ||||
| -rw-r--r-- | hw/devices.h | 3 | ||||
| -rw-r--r-- | hw/pci.c | 13 | ||||
| -rw-r--r-- | hw/ppc_oldworld.c | 13 | ||||
| -rw-r--r-- | hw/ppc_prep.c | 107 | ||||
| -rw-r--r-- | hw/ppce500_mpc8544ds.c | 5 | ||||
| -rw-r--r-- | hw/pxa.h | 6 | ||||
| -rw-r--r-- | hw/pxa2xx.c | 264 | ||||
| -rw-r--r-- | hw/r2d.c | 35 | ||||
| -rw-r--r-- | hw/realview.c | 54 | ||||
| -rw-r--r-- | hw/s390-virtio.c | 8 | ||||
| -rw-r--r-- | hw/sm501.c | 143 | ||||
| -rw-r--r-- | hw/spapr.c | 9 | ||||
| -rw-r--r-- | hw/spitz.c | 48 | ||||
| -rw-r--r-- | hw/strongarm.c | 171 | ||||
| -rw-r--r-- | hw/strongarm.h | 6 | ||||
| -rw-r--r-- | hw/sun4m.c | 49 | ||||
| -rw-r--r-- | hw/sun4u.c | 22 | ||||
| -rw-r--r-- | hw/syborg.c | 8 | ||||
| -rw-r--r-- | hw/tc6393xb.c | 71 | ||||
| -rw-r--r-- | hw/tcx.c | 152 | ||||
| -rw-r--r-- | hw/tosa.c | 2 |
22 files changed, 544 insertions, 649 deletions
diff --git a/hw/collie.c b/hw/collie.c index a10cc1b90c..8dd6e4ec7e 100644 --- a/hw/collie.c +++ b/hw/collie.c @@ -13,6 +13,7 @@ #include "arm-misc.h" #include "flash.h" #include "blockdev.h" +#include "exec-memory.h" static struct arm_boot_info collie_binfo = { .loader_start = SA_SDCS0, @@ -26,12 +27,13 @@ static void collie_init(ram_addr_t ram_size, { StrongARMState *s; DriveInfo *dinfo; + MemoryRegion *sysmem = get_system_memory(); if (!cpu_model) { cpu_model = "sa1110"; } - s = sa1110_init(collie_binfo.ram_size, cpu_model); + s = sa1110_init(sysmem, collie_binfo.ram_size, cpu_model); dinfo = drive_get(IF_PFLASH, 0, 0); pflash_cfi01_register(SA_CS0, NULL, "collie.fl1", 0x02000000, diff --git a/hw/devices.h b/hw/devices.h index 8ac384ff20..1a55c1e905 100644 --- a/hw/devices.h +++ b/hw/devices.h @@ -53,7 +53,8 @@ void retu_key_event(void *retu, int state); /* tc6393xb.c */ typedef struct TC6393xbState TC6393xbState; #define TC6393XB_RAM 0x110000 /* amount of ram for Video and USB */ -TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq); +TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, + uint32_t base, qemu_irq irq); void tc6393xb_gpio_out_set(TC6393xbState *s, int line, qemu_irq handler); qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s); @@ -998,17 +998,8 @@ static void pci_update_mappings(PCIDevice *d) } r->addr = new_addr; if (r->addr != PCI_BAR_UNMAPPED) { - if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { - memory_region_add_subregion_overlap(r->address_space, - r->addr, - r->memory, - 1); - } else { - memory_region_add_subregion_overlap(r->address_space, - r->addr, - r->memory, - 1); - } + memory_region_add_subregion_overlap(r->address_space, + r->addr, r->memory, 1); } } } diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index ebcaafa641..aac3526f55 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -73,11 +73,13 @@ static void ppc_heathrow_init (ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { + MemoryRegion *sysmem = get_system_memory(); CPUState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; int linux_boot, i; - ram_addr_t ram_offset, bios_offset; + MemoryRegion *ram = g_new(MemoryRegion, 1); + MemoryRegion *bios = g_new(MemoryRegion, 1); uint32_t kernel_base, initrd_base, cmdline_base = 0; int32_t kernel_size, initrd_size; PCIBus *pci_bus; @@ -114,15 +116,16 @@ static void ppc_heathrow_init (ram_addr_t ram_size, exit(1); } - ram_offset = qemu_ram_alloc(NULL, "ppc_heathrow.ram", ram_size); - cpu_register_physical_memory(0, ram_size, ram_offset); + memory_region_init_ram(ram, NULL, "ppc_heathrow.ram", ram_size); + memory_region_add_subregion(sysmem, 0, ram); /* allocate and load BIOS */ - bios_offset = qemu_ram_alloc(NULL, "ppc_heathrow.bios", BIOS_SIZE); + memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = PROM_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); - cpu_register_physical_memory(PROM_ADDR, BIOS_SIZE, bios_offset | IO_MEM_ROM); + memory_region_set_readonly(bios, true); + memory_region_add_subregion(sysmem, PROM_ADDR, bios); /* Load OpenBIOS (ELF) */ if (filename) { diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index 6427baa562..f22d5b98c5 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -116,16 +116,17 @@ static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) /* PCI intack register */ /* Read-only register (?) */ -static void _PPC_intack_write (void *opaque, - target_phys_addr_t addr, uint32_t value) +static void PPC_intack_write (void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { #if 0 - printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr, + printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx64 "\n", __func__, addr, value); #endif } -static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) +static uint64_t PPC_intack_read(void *opaque, target_phys_addr_t addr, + unsigned size) { uint32_t retval = 0; @@ -139,31 +140,10 @@ static inline uint32_t _PPC_intack_read(target_phys_addr_t addr) return retval; } -static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) -{ - return _PPC_intack_read(addr); -} - -static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) -{ - return _PPC_intack_read(addr); -} - -static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) -{ - return _PPC_intack_read(addr); -} - -static CPUWriteMemoryFunc * const PPC_intack_write[] = { - &_PPC_intack_write, - &_PPC_intack_write, - &_PPC_intack_write, -}; - -static CPUReadMemoryFunc * const PPC_intack_read[] = { - &PPC_intack_readb, - &PPC_intack_readw, - &PPC_intack_readl, +static const MemoryRegionOps PPC_intack_ops = { + .read = PPC_intack_read, + .write = PPC_intack_write, + .endianness = DEVICE_LITTLE_ENDIAN, }; /* PowerPC control and status registers */ @@ -244,17 +224,14 @@ static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) return retval; } -static CPUWriteMemoryFunc * const PPC_XCSR_write[] = { - &PPC_XCSR_writeb, - &PPC_XCSR_writew, - &PPC_XCSR_writel, +static const MemoryRegionOps PPC_XCSR_ops = { + .old_mmio = { + .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, }, + .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, }, + }, + .endianness = DEVICE_LITTLE_ENDIAN, }; -static CPUReadMemoryFunc * const PPC_XCSR_read[] = { - &PPC_XCSR_readb, - &PPC_XCSR_readw, - &PPC_XCSR_readl, -}; #endif /* Fake super-io ports for PREP platform (Intel 82378ZB) */ @@ -503,16 +480,12 @@ static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) return ret; } -static CPUWriteMemoryFunc * const PPC_prep_io_write[] = { - &PPC_prep_io_writeb, - &PPC_prep_io_writew, - &PPC_prep_io_writel, -}; - -static CPUReadMemoryFunc * const PPC_prep_io_read[] = { - &PPC_prep_io_readb, - &PPC_prep_io_readw, - &PPC_prep_io_readl, +static const MemoryRegionOps PPC_prep_io_ops = { + .old_mmio = { + .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl }, + .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel }, + }, + .endianness = DEVICE_LITTLE_ENDIAN, }; #define NVRAM_SIZE 0x2000 @@ -534,13 +507,19 @@ static void ppc_prep_init (ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { + MemoryRegion *sysmem = get_system_memory(); CPUState *env = NULL; char *filename; nvram_t nvram; M48t59State *m48t59; - int PPC_io_memory; + MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1); + MemoryRegion *intack = g_new(MemoryRegion, 1); +#if 0 + MemoryRegion *xcsr = g_new(MemoryRegion, 1); +#endif int linux_boot, i, nb_nics1, bios_size; - ram_addr_t ram_offset, bios_offset; + MemoryRegion *ram = g_new(MemoryRegion, 1); + MemoryRegion *bios = g_new(MemoryRegion, 1); uint32_t kernel_base, initrd_base; long kernel_size, initrd_size; PCIBus *pci_bus; @@ -574,11 +553,11 @@ static void ppc_prep_init (ram_addr_t ram_size, } /* allocate RAM */ - ram_offset = qemu_ram_alloc(NULL, "ppc_prep.ram", ram_size); - cpu_register_physical_memory(0, ram_size, ram_offset); + memory_region_init_ram(ram, NULL, "ppc_prep.ram", ram_size); + memory_region_add_subregion(sysmem, 0, ram); /* allocate and load BIOS */ - bios_offset = qemu_ram_alloc(NULL, "ppc_prep.bios", BIOS_SIZE); + memory_region_init_ram(bios, NULL, "ppc_prep.bios", BIOS_SIZE); if (bios_name == NULL) bios_name = BIOS_FILENAME; filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); @@ -591,8 +570,8 @@ static void ppc_prep_init (ram_addr_t ram_size, target_phys_addr_t bios_addr; bios_size = (bios_size + 0xfff) & ~0xfff; bios_addr = (uint32_t)(-bios_size); - cpu_register_physical_memory(bios_addr, bios_size, - bios_offset | IO_MEM_ROM); + memory_region_set_readonly(bios, true); + memory_region_add_subregion(sysmem, bios_addr, bios); bios_size = load_image_targphys(filename, bios_addr, bios_size); } if (bios_size < 0 || bios_size > BIOS_SIZE) { @@ -655,10 +634,9 @@ static void ppc_prep_init (ram_addr_t ram_size, isa_bus_irqs(i8259); // pci_bus = i440fx_init(); /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ - PPC_io_memory = cpu_register_io_memory(PPC_prep_io_read, - PPC_prep_io_write, sysctrl, - DEVICE_LITTLE_ENDIAN); - cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); + memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl, + "ppc-io", 0x00800000); + memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); /* init basic PC hardware */ pci_vga_init(pci_bus); @@ -713,15 +691,12 @@ static void ppc_prep_init (ram_addr_t ram_size, register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); /* PCI intack location */ - PPC_io_memory = cpu_register_io_memory(PPC_intack_read, - PPC_intack_write, NULL, - DEVICE_LITTLE_ENDIAN); - cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); + memory_region_init_io(intack, &PPC_intack_ops, NULL, "ppc-intack", 4); + memory_region_add_subregion(sysmem, 0xBFFFFFF0, intack); /* PowerPC control and status register group */ #if 0 - PPC_io_memory = cpu_register_io_memory(PPC_XCSR_read, PPC_XCSR_write, - NULL, DEVICE_LITTLE_ENDIAN); - cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory); + memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000); + memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr); #endif if (usb_enabled) { diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index 5bf8eab897..51b6abddd3 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -229,6 +229,7 @@ static void mpc8544ds_init(ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *ram = g_new(MemoryRegion, 1); PCIBus *pci_bus; CPUState *env = NULL; uint64_t elf_entry; @@ -291,8 +292,8 @@ static void mpc8544ds_init(ram_addr_t ram_size, ram_size &= ~(RAM_SIZES_ALIGN - 1); /* Register Memory */ - cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL, - "mpc8544ds.ram", ram_size)); + memory_region_init_ram(ram, NULL, "mpc8544ds.ram", ram_size); + memory_region_add_subregion(address_space_mem, 0, ram); /* MPIC */ mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE, @@ -122,6 +122,11 @@ typedef struct { CPUState *env; DeviceState *pic; qemu_irq reset; + MemoryRegion sdram; + MemoryRegion internal; + MemoryRegion cm_iomem; + MemoryRegion mm_iomem; + MemoryRegion pm_iomem; DeviceState *dma; DeviceState *gpio; PXA2xxLCDState *lcd; @@ -151,6 +156,7 @@ typedef struct { } PXA2xxState; struct PXA2xxI2SState { + MemoryRegion iomem; qemu_irq irq; qemu_irq rx_dma; qemu_irq tx_dma; diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 70d7c8a06d..bfc28a999b 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -88,7 +88,8 @@ static PXASSPDef pxa27x_ssp[] = { #define PCMD0 0x80 /* Power Manager I2C Command register File 0 */ #define PCMD31 0xfc /* Power Manager I2C Command register File 31 */ -static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -107,7 +108,7 @@ static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -134,16 +135,10 @@ static void pxa2xx_pm_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_pm_readfn[] = { - pxa2xx_pm_read, - pxa2xx_pm_read, - pxa2xx_pm_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_pm_writefn[] = { - pxa2xx_pm_write, - pxa2xx_pm_write, - pxa2xx_pm_write, +static const MemoryRegionOps pxa2xx_pm_ops = { + .read = pxa2xx_pm_read, + .write = pxa2xx_pm_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_pxa2xx_pm = { @@ -162,7 +157,8 @@ static const VMStateDescription vmstate_pxa2xx_pm = { #define OSCC 0x08 /* Oscillator Configuration register */ #define CCSR 0x0c /* Core Clock Status register */ -static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -183,7 +179,7 @@ static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -206,16 +202,10 @@ static void pxa2xx_cm_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_cm_readfn[] = { - pxa2xx_cm_read, - pxa2xx_cm_read, - pxa2xx_cm_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_cm_writefn[] = { - pxa2xx_cm_write, - pxa2xx_cm_write, - pxa2xx_cm_write, +static const MemoryRegionOps pxa2xx_cm_ops = { + .read = pxa2xx_cm_read, + .write = pxa2xx_cm_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_pxa2xx_cm = { @@ -461,7 +451,8 @@ static void pxa2xx_cp14_write(void *opaque, int op2, int reg, int crm, #define BSCNTR3 0x60 /* Memory Buffer Strength Control register 3 */ #define SA1110 0x64 /* SA-1110 Memory Compatibility register */ -static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -478,7 +469,7 @@ static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { PXA2xxState *s = (PXA2xxState *) opaque; @@ -495,16 +486,10 @@ static void pxa2xx_mm_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_mm_readfn[] = { - pxa2xx_mm_read, - pxa2xx_mm_read, - pxa2xx_mm_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_mm_writefn[] = { - pxa2xx_mm_write, - pxa2xx_mm_write, - pxa2xx_mm_write, +static const MemoryRegionOps pxa2xx_mm_ops = { + .read = pxa2xx_mm_read, + .write = pxa2xx_mm_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_pxa2xx_mm = { @@ -521,6 +506,7 @@ static const VMStateDescription vmstate_pxa2xx_mm = { /* Synchronous Serial Ports */ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq irq; int enable; SSIBus *bus; @@ -627,7 +613,8 @@ static void pxa2xx_ssp_fifo_update(PXA2xxSSPState *s) pxa2xx_ssp_int_update(s); } -static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; uint32_t retval; @@ -673,9 +660,10 @@ static uint32_t pxa2xx_ssp_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value64, unsigned size) { PXA2xxSSPState *s = (PXA2xxSSPState *) opaque; + uint32_t value = value64; switch (addr) { case SSCR0: @@ -762,16 +750,10 @@ static void pxa2xx_ssp_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_ssp_readfn[] = { - pxa2xx_ssp_read, - pxa2xx_ssp_read, - pxa2xx_ssp_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_ssp_writefn[] = { - pxa2xx_ssp_write, - pxa2xx_ssp_write, - pxa2xx_ssp_write, +static const MemoryRegionOps pxa2xx_ssp_ops = { + .read = pxa2xx_ssp_read, + .write = pxa2xx_ssp_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void pxa2xx_ssp_save(QEMUFile *f, void *opaque) @@ -823,15 +805,12 @@ static int pxa2xx_ssp_load(QEMUFile *f, void *opaque, int version_id) static int pxa2xx_ssp_init(SysBusDevice *dev) { - int iomemtype; PXA2xxSSPState *s = FROM_SYSBUS(PXA2xxSSPState, dev); sysbus_init_irq(dev, &s->irq); - iomemtype = cpu_register_io_memory(pxa2xx_ssp_readfn, - pxa2xx_ssp_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_ssp_ops, s, "pxa2xx-ssp", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); register_savevm(&dev->qdev, "pxa2xx_ssp", -1, 0, pxa2xx_ssp_save, pxa2xx_ssp_load, s); @@ -858,6 +837,7 @@ static int pxa2xx_ssp_init(SysBusDevice *dev) typedef struct { SysBusDevice busdev; + MemoryRegion iomem; uint32_t rttr; uint32_t rtsr; uint32_t rtar; @@ -1009,7 +989,8 @@ static inline void pxa2xx_rtc_pi_tick(void *opaque) pxa2xx_rtc_int_update(s); } -static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; @@ -1055,9 +1036,10 @@ static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value64, unsigned size) { PXA2xxRTCState *s = (PXA2xxRTCState *) opaque; + uint32_t value = value64; switch (addr) { case RTTR: @@ -1157,16 +1139,10 @@ static void pxa2xx_rtc_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_rtc_readfn[] = { - pxa2xx_rtc_read, - pxa2xx_rtc_read, - pxa2xx_rtc_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_rtc_writefn[] = { - pxa2xx_rtc_write, - pxa2xx_rtc_write, - pxa2xx_rtc_write, +static const MemoryRegionOps pxa2xx_rtc_ops = { + .read = pxa2xx_rtc_read, + .write = pxa2xx_rtc_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int pxa2xx_rtc_init(SysBusDevice *dev) @@ -1174,7 +1150,6 @@ static int pxa2xx_rtc_init(SysBusDevice *dev) PXA2xxRTCState *s = FROM_SYSBUS(PXA2xxRTCState, dev); struct tm tm; int wom; - int iomemtype; s->rttr = 0x7fff; s->rtsr = 0; @@ -1201,9 +1176,8 @@ static int pxa2xx_rtc_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->rtc_irq); - iomemtype = cpu_register_io_memory(pxa2xx_rtc_readfn, - pxa2xx_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x10000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_rtc_ops, s, "pxa2xx-rtc", 0x10000); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } @@ -1272,6 +1246,7 @@ typedef struct { struct PXA2xxI2CState { SysBusDevice busdev; + MemoryRegion iomem; PXA2xxI2CSlaveState *slave; i2c_bus *bus; qemu_irq irq; @@ -1356,7 +1331,8 @@ static int pxa2xx_i2c_tx(i2c_slave *i2c, uint8_t data) return 1; } -static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; @@ -1384,9 +1360,10 @@ static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value64, unsigned size) { PXA2xxI2CState *s = (PXA2xxI2CState *) opaque; + uint32_t value = value64; int ack; addr -= s->offset; @@ -1453,16 +1430,10 @@ static void pxa2xx_i2c_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_i2c_readfn[] = { - pxa2xx_i2c_read, - pxa2xx_i2c_read, - pxa2xx_i2c_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_i2c_writefn[] = { - pxa2xx_i2c_write, - pxa2xx_i2c_write, - pxa2xx_i2c_write, +static const MemoryRegionOps pxa2xx_i2c_ops = { + .read = pxa2xx_i2c_read, + .write = pxa2xx_i2c_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_pxa2xx_i2c_slave = { @@ -1536,13 +1507,12 @@ PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base, static int pxa2xx_i2c_initfn(SysBusDevice *dev) { PXA2xxI2CState *s = FROM_SYSBUS(PXA2xxI2CState, dev); - int iomemtype; s->bus = i2c_init_bus(&dev->qdev, "i2c"); - iomemtype = cpu_register_io_memory(pxa2xx_i2c_readfn, - pxa2xx_i2c_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, s->region_size, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_i2c_ops, s, + "pxa2xx-i2x", s->region_size); + sysbus_init_mmio_region(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); return 0; @@ -1621,7 +1591,8 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) #define SADIV 0x60 /* Serial Audio Clock Divider register */ #define SADR 0x80 /* Serial Audio Data register */ -static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; @@ -1653,7 +1624,7 @@ static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { PXA2xxI2SState *s = (PXA2xxI2SState *) opaque; uint32_t *sample; @@ -1707,16 +1678,10 @@ static void pxa2xx_i2s_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_i2s_readfn[] = { - pxa2xx_i2s_read, - pxa2xx_i2s_read, - pxa2xx_i2s_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_i2s_writefn[] = { - pxa2xx_i2s_write, - pxa2xx_i2s_write, - pxa2xx_i2s_write, +static const MemoryRegionOps pxa2xx_i2s_ops = { + .read = pxa2xx_i2s_read, + .write = pxa2xx_i2s_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static const VMStateDescription vmstate_pxa2xx_i2s = { @@ -1759,10 +1724,10 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) pxa2xx_i2s_update(s); } -static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, +static PXA2xxI2SState *pxa2xx_i2s_init(MemoryRegion *sysmem, + target_phys_addr_t base, qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) { - int iomemtype; PXA2xxI2SState *s = (PXA2xxI2SState *) g_malloc0(sizeof(PXA2xxI2SState)); @@ -1773,9 +1738,9 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, pxa2xx_i2s_reset(s); - iomemtype = cpu_register_io_memory(pxa2xx_i2s_readfn, - pxa2xx_i2s_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x100000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_i2s_ops, s, + "pxa2xx-i2s", 0x100000); + memory_region_add_subregion(sysmem, base, &s->iomem); vmstate_register(NULL, base, &vmstate_pxa2xx_i2s, s); @@ -1784,6 +1749,7 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, /* PXA Fast Infra-red Communications Port */ struct PXA2xxFIrState { + MemoryRegion iomem; qemu_irq irq; qemu_irq rx_dma; qemu_irq tx_dma; @@ -1854,7 +1820,8 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s) #define ICSR1 0x18 /* FICP Status register 1 */ #define ICFOR 0x1c /* FICP FIFO Occupancy Status register */ -static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) +static uint64_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr, + unsigned size) { PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; uint8_t ret; @@ -1892,9 +1859,10 @@ static uint32_t pxa2xx_fir_read(void *opaque, target_phys_addr_t addr) } static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value64, unsigned size) { PXA2xxFIrState *s = (PXA2xxFIrState *) opaque; + uint32_t value = value64; uint8_t ch; switch (addr) { @@ -1936,16 +1904,10 @@ static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const pxa2xx_fir_readfn[] = { - pxa2xx_fir_read, - pxa2xx_fir_read, - pxa2xx_fir_read, -}; - -static CPUWriteMemoryFunc * const pxa2xx_fir_writefn[] = { - pxa2xx_fir_write, - pxa2xx_fir_write, - pxa2xx_fir_write, +static const MemoryRegionOps pxa2xx_fir_ops = { + .read = pxa2xx_fir_read, + .write = pxa2xx_fir_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int pxa2xx_fir_is_empty(void *opaque) @@ -2019,11 +1981,11 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) return 0; } -static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, +static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem, + target_phys_addr_t base, qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, CharDriverState *chr) { - int iomemtype; PXA2xxFIrState *s = (PXA2xxFIrState *) g_malloc0(sizeof(PXA2xxFIrState)); @@ -2034,9 +1996,8 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, pxa2xx_fir_reset(s); - iomemtype = cpu_register_io_memory(pxa2xx_fir_readfn, - pxa2xx_fir_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000); + memory_region_add_subregion(sysmem, base, &s->iomem); if (chr) qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty, @@ -2063,7 +2024,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, const char *revision) { PXA2xxState *s; - int iomemtype, i; + int i; DriveInfo *dinfo; s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); @@ -2082,12 +2043,11 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; /* SDRAM & Internal Memory Storage */ - cpu_register_physical_memory(PXA2XX_SDRAM_BASE, - sdram_size, qemu_ram_alloc(NULL, "pxa270.sdram", - sdram_size) | IO_MEM_RAM); - cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, - 0x40000, qemu_ram_alloc(NULL, "pxa270.internal", - 0x40000) | IO_MEM_RAM); + memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size); + memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); + memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000); + memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, + &s->internal); s->pic = pxa2xx_pic_init(0x40d00000, s->env); @@ -2125,7 +2085,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, } } if (serial_hds[i]) - s->fir = pxa2xx_fir_init(0x40800000, + s->fir = pxa2xx_fir_init(address_space, 0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), @@ -2137,9 +2097,8 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, s->cm_base = 0x41300000; s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ s->clkcfg = 0x00000009; /* Turbo mode active */ - iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn, - pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype); + memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); + memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); @@ -2148,15 +2107,13 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, s->mm_regs[MDMRS >> 2] = 0x00020002; s->mm_regs[MDREFR >> 2] = 0x03ca4000; s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ - iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn, - pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype); + memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); + memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); s->pm_base = 0x40f00000; - iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn, - pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(s->pm_base, 0x100, iomemtype); + memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); + memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); for (i = 0; pxa27x_ssp[i].io_base; i ++); @@ -2184,7 +2141,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, s->i2c[1] = pxa2xx_i2c_init(0x40f00100, qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); - s->i2s = pxa2xx_i2s_init(0x40400000, + s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); @@ -2202,7 +2159,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) { PXA2xxState *s; - int iomemtype, i; + int i; DriveInfo *dinfo; s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); @@ -2215,12 +2172,12 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0]; /* SDRAM & Internal Memory Storage */ - cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size, - qemu_ram_alloc(NULL, "pxa255.sdram", - sdram_size) | IO_MEM_RAM); - cpu_register_physical_memory(PXA2XX_INTERNAL_BASE, PXA2XX_INTERNAL_SIZE, - qemu_ram_alloc(NULL, "pxa255.internal", - PXA2XX_INTERNAL_SIZE) | IO_MEM_RAM); + memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size); + memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); + memory_region_init_ram(&s->internal, NULL, "pxa255.internal", + PXA2XX_INTERNAL_SIZE); + memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, + &s->internal); s->pic = pxa2xx_pic_init(0x40d00000, s->env); @@ -2257,7 +2214,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) } } if (serial_hds[i]) - s->fir = pxa2xx_fir_init(0x40800000, + s->fir = pxa2xx_fir_init(address_space, 0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), @@ -2269,9 +2226,8 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s->cm_base = 0x41300000; s->cm_regs[CCCR >> 2] = 0x02000210; /* 416.0 MHz */ s->clkcfg = 0x00000009; /* Turbo mode active */ - iomemtype = cpu_register_io_memory(pxa2xx_cm_readfn, - pxa2xx_cm_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(s->cm_base, 0x1000, iomemtype); + memory_region_init_io(&s->cm_iomem, &pxa2xx_cm_ops, s, "pxa2xx-cm", 0x1000); + memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); @@ -2280,15 +2236,13 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s->mm_regs[MDMRS >> 2] = 0x00020002; s->mm_regs[MDREFR >> 2] = 0x03ca4000; s->mm_regs[MECR >> 2] = 0x00000001; /* Two PC Card sockets */ - iomemtype = cpu_register_io_memory(pxa2xx_mm_readfn, - pxa2xx_mm_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(s->mm_base, 0x1000, iomemtype); + memory_region_init_io(&s->mm_iomem, &pxa2xx_mm_ops, s, "pxa2xx-mm", 0x1000); + memory_region_add_subregion(address_space, s->mm_base, &s->mm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_mm, s); s->pm_base = 0x40f00000; - iomemtype = cpu_register_io_memory(pxa2xx_pm_readfn, - pxa2xx_pm_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(s->pm_base, 0x100, iomemtype); + memory_region_init_io(&s->pm_iomem, &pxa2xx_pm_ops, s, "pxa2xx-pm", 0x100); + memory_region_add_subregion(address_space, s->pm_base, &s->pm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_pm, s); for (i = 0; pxa255_ssp[i].io_base; i ++); @@ -2316,7 +2270,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s->i2c[1] = pxa2xx_i2c_init(0x40f00100, qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); - s->i2s = pxa2xx_i2s_init(0x40400000, + s->i2s = pxa2xx_i2s_init(address_space, 0x40400000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); @@ -82,6 +82,7 @@ typedef struct { /* output pin */ qemu_irq irl; + MemoryRegion iomem; } r2d_fpga_t; enum r2d_fpga_irq { @@ -168,31 +169,25 @@ r2d_fpga_write(void *opaque, target_phys_addr_t addr, uint32_t value) } } -static CPUReadMemoryFunc * const r2d_fpga_readfn[] = { - r2d_fpga_read, - r2d_fpga_read, - NULL, +static const MemoryRegionOps r2d_fpga_ops = { + .old_mmio = { + .read = { r2d_fpga_read, r2d_fpga_read, NULL, }, + .write = { r2d_fpga_write, r2d_fpga_write, NULL, }, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const r2d_fpga_writefn[] = { - r2d_fpga_write, - r2d_fpga_write, - NULL, -}; - -static qemu_irq *r2d_fpga_init(target_phys_addr_t base, qemu_irq irl) +static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, + target_phys_addr_t base, qemu_irq irl) { - int iomemtype; r2d_fpga_t *s; s = g_malloc0(sizeof(r2d_fpga_t)); s->irl = irl; - iomemtype = cpu_register_io_memory(r2d_fpga_readfn, - r2d_fpga_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x40, iomemtype); + memory_region_init_io(&s->iomem, &r2d_fpga_ops, s, "r2d-fpga", 0x40); + memory_region_add_subregion(sysmem, base, &s->iomem); return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); } @@ -232,7 +227,7 @@ static void r2d_init(ram_addr_t ram_size, CPUState *env; ResetData *reset_info; struct SH7750State *s; - ram_addr_t sdram_addr; + MemoryRegion *sdram = g_new(MemoryRegion, 1); qemu_irq *irq; DriveInfo *dinfo; int i; @@ -252,11 +247,11 @@ static void r2d_init(ram_addr_t ram_size, qemu_register_reset(main_cpu_reset, reset_info); /* Allocate memory space */ - sdram_addr = qemu_ram_alloc(NULL, "r2d.sdram", SDRAM_SIZE); - cpu_register_physical_memory(SDRAM_BASE, SDRAM_SIZE, sdram_addr); + memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE); + memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); /* Register peripherals */ s = sh7750_init(env); - irq = r2d_fpga_init(0x04000000, sh7750_irl(s)); + irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); sysbus_create_varargs("sh_pci", 0x1e200000, irq[PCI_INTA], irq[PCI_INTB], irq[PCI_INTC], irq[PCI_INTD], NULL); diff --git a/hw/realview.c b/hw/realview.c index 11ffb8a824..14281b0f06 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -18,17 +18,20 @@ #include "boards.h" #include "bitbang_i2c.h" #include "blockdev.h" +#include "exec-memory.h" #define SMP_BOOT_ADDR 0xe0000000 typedef struct { SysBusDevice busdev; + MemoryRegion iomem; bitbang_i2c_interface *bitbang; int out; int in; } RealViewI2CState; -static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset) +static uint64_t realview_i2c_read(void *opaque, target_phys_addr_t offset, + unsigned size) { RealViewI2CState *s = (RealViewI2CState *)opaque; @@ -41,7 +44,7 @@ static uint32_t realview_i2c_read(void *opaque, target_phys_addr_t offset) } static void realview_i2c_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { RealViewI2CState *s = (RealViewI2CState *)opaque; @@ -59,30 +62,22 @@ static void realview_i2c_write(void *opaque, target_phys_addr_t offset, s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); } -static CPUReadMemoryFunc * const realview_i2c_readfn[] = { - realview_i2c_read, - realview_i2c_read, - realview_i2c_read -}; - -static CPUWriteMemoryFunc * const realview_i2c_writefn[] = { - realview_i2c_write, - realview_i2c_write, - realview_i2c_write +static const MemoryRegionOps realview_i2c_ops = { + .read = realview_i2c_read, + .write = realview_i2c_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int realview_i2c_init(SysBusDevice *dev) { RealViewI2CState *s = FROM_SYSBUS(RealViewI2CState, dev); i2c_bus *bus; - int iomemtype; bus = i2c_init_bus(&dev->qdev, "i2c"); s->bitbang = bitbang_i2c_init(bus); - iomemtype = cpu_register_io_memory(realview_i2c_readfn, - realview_i2c_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &realview_i2c_ops, s, + "realview-i2c", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } @@ -125,7 +120,11 @@ static void realview_init(ram_addr_t ram_size, enum realview_board_type board_type) { CPUState *env = NULL; - ram_addr_t ram_offset; + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *ram_lo = g_new(MemoryRegion, 1); + MemoryRegion *ram_hi = g_new(MemoryRegion, 1); + MemoryRegion *ram_alias = g_new(MemoryRegion, 1); + MemoryRegion *ram_hack = g_new(MemoryRegion, 1); DeviceState *dev, *sysctl, *gpio2; SysBusDevice *busdev; qemu_irq *irqp; @@ -184,21 +183,21 @@ static void realview_init(ram_addr_t ram_size, /* Core tile RAM. */ low_ram_size = ram_size - 0x20000000; ram_size = 0x20000000; - ram_offset = qemu_ram_alloc(NULL, "realview.lowmem", low_ram_size); - cpu_register_physical_memory(0x20000000, low_ram_size, - ram_offset | IO_MEM_RAM); + memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size); + memory_region_add_subregion(sysmem, 0x20000000, ram_lo); } - ram_offset = qemu_ram_alloc(NULL, "realview.highmem", ram_size); + memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size); low_ram_size = ram_size; if (low_ram_size > 0x10000000) low_ram_size = 0x10000000; /* SDRAM at address zero. */ - cpu_register_physical_memory(0, low_ram_size, ram_offset | IO_MEM_RAM); + memory_region_init_alias(ram_alias, "realview.alias", + ram_hi, 0, low_ram_size); + memory_region_add_subregion(sysmem, 0, ram_alias); if (is_pb) { /* And again at a high address. */ - cpu_register_physical_memory(0x70000000, ram_size, - ram_offset | IO_MEM_RAM); + memory_region_add_subregion(sysmem, 0x70000000, ram_hi); } else { ram_size = low_ram_size; } @@ -372,9 +371,8 @@ static void realview_init(ram_addr_t ram_size, startup code. I guess this works on real hardware because the BootROM happens to be in ROM/flash or in memory that isn't clobbered until after Linux boots the secondary CPUs. */ - ram_offset = qemu_ram_alloc(NULL, "realview.hack", 0x1000); - cpu_register_physical_memory(SMP_BOOT_ADDR, 0x1000, - ram_offset | IO_MEM_RAM); + memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000); + memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); realview_binfo.ram_size = ram_size; realview_binfo.kernel_filename = kernel_filename; diff --git a/hw/s390-virtio.c b/hw/s390-virtio.c index 778cffe39c..60c66e92c4 100644 --- a/hw/s390-virtio.c +++ b/hw/s390-virtio.c @@ -29,6 +29,7 @@ #include "hw/virtio.h" #include "hw/sysbus.h" #include "kvm.h" +#include "exec-memory.h" #include "hw/s390-virtio-bus.h" @@ -128,7 +129,8 @@ static void s390_init(ram_addr_t my_ram_size, const char *cpu_model) { CPUState *env = NULL; - ram_addr_t ram_addr; + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *ram = g_new(MemoryRegion, 1); ram_addr_t kernel_size = 0; ram_addr_t initrd_offset; ram_addr_t initrd_size = 0; @@ -150,8 +152,8 @@ static void s390_init(ram_addr_t my_ram_size, s390_bus = s390_virtio_bus_init(&my_ram_size); /* allocate RAM */ - ram_addr = qemu_ram_alloc(NULL, "s390.ram", my_ram_size); - cpu_register_physical_memory(0, my_ram_size, ram_addr); + memory_region_init_ram(ram, NULL, "s390.ram", my_ram_size); + memory_region_add_subregion(sysmem, 0, ram); /* allocate storage keys */ storage_keys = g_malloc0(my_ram_size / TARGET_PAGE_SIZE); diff --git a/hw/sm501.c b/hw/sm501.c index a7ed6fadf1..297bc9c318 100644 --- a/hw/sm501.c +++ b/hw/sm501.c @@ -459,7 +459,7 @@ typedef struct SM501State { target_phys_addr_t base; uint32_t local_mem_size_index; uint8_t * local_mem; - ram_addr_t local_mem_offset; + MemoryRegion local_mem_region; uint32_t last_width; uint32_t last_height; @@ -726,7 +726,8 @@ static void sm501_2d_operation(SM501State * s) } } -static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr) +static uint64_t sm501_system_config_read(void *opaque, target_phys_addr_t addr, + unsigned size) { SM501State * s = (SM501State *)opaque; uint32_t ret = 0; @@ -778,12 +779,12 @@ static uint32_t sm501_system_config_read(void *opaque, target_phys_addr_t addr) return ret; } -static void sm501_system_config_write(void *opaque, - target_phys_addr_t addr, uint32_t value) +static void sm501_system_config_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { SM501State * s = (SM501State *)opaque; SM501_DPRINTF("sm501 system config regs : write addr=%x, val=%x\n", - addr, value); + (uint32_t)addr, (uint32_t)value); switch(addr) { case SM501_SYSTEM_CONTROL: @@ -821,21 +822,19 @@ static void sm501_system_config_write(void *opaque, default: printf("sm501 system config : not implemented register write." - " addr=%x, val=%x\n", (int)addr, value); + " addr=%x, val=%x\n", (int)addr, (uint32_t)value); abort(); } } -static CPUReadMemoryFunc * const sm501_system_config_readfn[] = { - NULL, - NULL, - &sm501_system_config_read, -}; - -static CPUWriteMemoryFunc * const sm501_system_config_writefn[] = { - NULL, - NULL, - &sm501_system_config_write, +static const MemoryRegionOps sm501_system_config_ops = { + .read = sm501_system_config_read, + .write = sm501_system_config_write, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; static uint32_t sm501_palette_read(void *opaque, target_phys_addr_t addr) @@ -864,7 +863,8 @@ static void sm501_palette_write(void *opaque, *(uint32_t*)&s->dc_palette[addr] = value; } -static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) +static uint64_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr, + unsigned size) { SM501State * s = (SM501State *)opaque; uint32_t ret = 0; @@ -958,13 +958,12 @@ static uint32_t sm501_disp_ctrl_read(void *opaque, target_phys_addr_t addr) return ret; } -static void sm501_disp_ctrl_write(void *opaque, - target_phys_addr_t addr, - uint32_t value) +static void sm501_disp_ctrl_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { SM501State * s = (SM501State *)opaque; SM501_DPRINTF("sm501 disp ctrl regs : write addr=%x, val=%x\n", - addr, value); + (unsigned)addr, (unsigned)value); switch(addr) { case SM501_DC_PANEL_CONTROL: @@ -1059,24 +1058,23 @@ static void sm501_disp_ctrl_write(void *opaque, default: printf("sm501 disp ctrl : not implemented register write." - " addr=%x, val=%x\n", (int)addr, value); + " addr=%x, val=%x\n", (int)addr, (unsigned)value); abort(); } } -static CPUReadMemoryFunc * const sm501_disp_ctrl_readfn[] = { - NULL, - NULL, - &sm501_disp_ctrl_read, -}; - -static CPUWriteMemoryFunc * const sm501_disp_ctrl_writefn[] = { - NULL, - NULL, - &sm501_disp_ctrl_write, +static const MemoryRegionOps sm501_disp_ctrl_ops = { + .read = sm501_disp_ctrl_read, + .write = sm501_disp_ctrl_write, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static uint32_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr) +static uint64_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr, + unsigned size) { SM501State * s = (SM501State *)opaque; uint32_t ret = 0; @@ -1095,12 +1093,12 @@ static uint32_t sm501_2d_engine_read(void *opaque, target_phys_addr_t addr) return ret; } -static void sm501_2d_engine_write(void *opaque, - target_phys_addr_t addr, uint32_t value) +static void sm501_2d_engine_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { SM501State * s = (SM501State *)opaque; SM501_DPRINTF("sm501 2d engine regs : write addr=%x, val=%x\n", - addr, value); + (unsigned)addr, (unsigned)value); switch(addr) { case SM501_2D_SOURCE: @@ -1148,21 +1146,19 @@ static void sm501_2d_engine_write(void *opaque, break; default: printf("sm501 2d engine : not implemented register write." - " addr=%x, val=%x\n", (int)addr, value); + " addr=%x, val=%x\n", (int)addr, (unsigned)value); abort(); } } -static CPUReadMemoryFunc * const sm501_2d_engine_readfn[] = { - NULL, - NULL, - &sm501_2d_engine_read, -}; - -static CPUWriteMemoryFunc * const sm501_2d_engine_writefn[] = { - NULL, - NULL, - &sm501_2d_engine_write, +static const MemoryRegionOps sm501_2d_engine_ops = { + .read = sm501_2d_engine_read, + .write = sm501_2d_engine_write, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, + .endianness = DEVICE_NATIVE_ENDIAN, }; /* draw line functions for all console modes */ @@ -1276,7 +1272,7 @@ static void sm501_draw_crt(SM501State * s) int y_start = -1; ram_addr_t page_min = ~0l; ram_addr_t page_max = 0l; - ram_addr_t offset = s->local_mem_offset; + ram_addr_t offset = 0; /* choose draw_line function */ switch (s->dc_crt_control & 3) { @@ -1333,7 +1329,8 @@ static void sm501_draw_crt(SM501State * s) /* check dirty flags for each line */ for (page = page0; page <= page1; page += TARGET_PAGE_SIZE) - if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) + if (memory_region_get_dirty(&s->local_mem_region, page, + DIRTY_MEMORY_VGA)) update = 1; /* draw line and change status */ @@ -1372,8 +1369,9 @@ static void sm501_draw_crt(SM501State * s) /* clear dirty flags */ if (page_min != ~0l) { - cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, - VGA_DIRTY_FLAG); + memory_region_reset_dirty(&s->local_mem_region, + page_min, page_max + TARGET_PAGE_SIZE, + DIRTY_MEMORY_VGA); } } @@ -1390,9 +1388,9 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base, { SM501State * s; DeviceState *dev; - int sm501_system_config_index; - int sm501_disp_ctrl_index; - int sm501_2d_engine_index; + MemoryRegion *sm501_system_config = g_new(MemoryRegion, 1); + MemoryRegion *sm501_disp_ctrl = g_new(MemoryRegion, 1); + MemoryRegion *sm501_2d_engine = g_new(MemoryRegion, 1); /* allocate management data region */ s = (SM501State *)g_malloc0(sizeof(SM501State)); @@ -1407,27 +1405,26 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base, s->dc_crt_control = 0x00010000; /* allocate local memory */ - s->local_mem_offset = qemu_ram_alloc(NULL, "sm501.local", local_mem_bytes); - s->local_mem = qemu_get_ram_ptr(s->local_mem_offset); - cpu_register_physical_memory(base, local_mem_bytes, s->local_mem_offset); + memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local", + local_mem_bytes); + s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); + memory_region_add_subregion(address_space_mem, base, &s->local_mem_region); /* map mmio */ - sm501_system_config_index - = cpu_register_io_memory(sm501_system_config_readfn, - sm501_system_config_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base + MMIO_BASE_OFFSET, - 0x6c, sm501_system_config_index); - sm501_disp_ctrl_index = cpu_register_io_memory(sm501_disp_ctrl_readfn, - sm501_disp_ctrl_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_DC, - 0x1000, sm501_disp_ctrl_index); - sm501_2d_engine_index = cpu_register_io_memory(sm501_2d_engine_readfn, - sm501_2d_engine_writefn, s, - DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base + MMIO_BASE_OFFSET + SM501_2D_ENGINE, - 0x54, sm501_2d_engine_index); + memory_region_init_io(sm501_system_config, &sm501_system_config_ops, s, + "sm501-system-config", 0x6c); + memory_region_add_subregion(address_space_mem, base + MMIO_BASE_OFFSET, + sm501_system_config); + memory_region_init_io(sm501_disp_ctrl, &sm501_disp_ctrl_ops, s, + "sm501-disp-ctrl", 0x1000); + memory_region_add_subregion(address_space_mem, + base + MMIO_BASE_OFFSET + SM501_DC, + sm501_disp_ctrl); + memory_region_init_io(sm501_2d_engine, &sm501_2d_engine_ops, s, + "sm501-2d-engine", 0x54); + memory_region_add_subregion(address_space_mem, + base + MMIO_BASE_OFFSET + SM501_2D_ENGINE, + sm501_2d_engine); /* bridge to usb host emulation module */ dev = qdev_create(NULL, "sysbus-ohci"); diff --git a/hw/spapr.c b/hw/spapr.c index b1189755d3..63e5d336ea 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -41,6 +41,8 @@ #include "kvm.h" #include "kvm_ppc.h" +#include "exec-memory.h" + #include <libfdt.h> #define KERNEL_LOAD_ADDR 0x00000000 @@ -324,7 +326,8 @@ static void ppc_spapr_init(ram_addr_t ram_size, { CPUState *env; int i; - ram_addr_t ram_offset; + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *ram = g_new(MemoryRegion, 1); uint32_t initrd_base; long kernel_size, initrd_size, fw_size; long pteg_shift = 17; @@ -361,8 +364,8 @@ static void ppc_spapr_init(ram_addr_t ram_size, /* allocate RAM */ spapr->ram_limit = ram_size; - ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", spapr->ram_limit); - cpu_register_physical_memory(0, ram_size, ram_offset); + memory_region_init_ram(ram, NULL, "ppc_spapr.ram", spapr->ram_limit); + memory_region_add_subregion(sysmem, 0, ram); /* allocate hash page table. For now we always make this 16mb, * later we should probably make it scale to the size of guest diff --git a/hw/spitz.c b/hw/spitz.c index 6f8a94ceb3..23f9d41ff7 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -49,6 +49,7 @@ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; DeviceState *nand; uint8_t ctl; uint8_t manf_id; @@ -56,7 +57,7 @@ typedef struct { ECCState ecc; } SLNANDState; -static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) +static uint64_t sl_read(void *opaque, target_phys_addr_t addr, unsigned size) { SLNANDState *s = (SLNANDState *) opaque; int ryby; @@ -86,6 +87,10 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) return s->ctl; case FLASH_FLASHIO: + if (size == 4) { + return ecc_digest(&s->ecc, nand_getio(s->nand)) | + (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16); + } return ecc_digest(&s->ecc, nand_getio(s->nand)); default: @@ -94,19 +99,8 @@ static uint32_t sl_readb(void *opaque, target_phys_addr_t addr) return 0; } -static uint32_t sl_readl(void *opaque, target_phys_addr_t addr) -{ - SLNANDState *s = (SLNANDState *) opaque; - - if (addr == FLASH_FLASHIO) - return ecc_digest(&s->ecc, nand_getio(s->nand)) | - (ecc_digest(&s->ecc, nand_getio(s->nand)) << 16); - - return sl_readb(opaque, addr); -} - -static void sl_writeb(void *opaque, target_phys_addr_t addr, - uint32_t value) +static void sl_write(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { SLNANDState *s = (SLNANDState *) opaque; @@ -140,15 +134,10 @@ enum { FLASH_1024M, }; -static CPUReadMemoryFunc * const sl_readfn[] = { - sl_readb, - sl_readb, - sl_readl, -}; -static CPUWriteMemoryFunc * const sl_writefn[] = { - sl_writeb, - sl_writeb, - sl_writeb, +static const MemoryRegionOps sl_ops = { + .read = sl_read, + .write = sl_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static void sl_flash_register(PXA2xxState *cpu, int size) @@ -168,7 +157,6 @@ static void sl_flash_register(PXA2xxState *cpu, int size) } static int sl_nand_init(SysBusDevice *dev) { - int iomemtype; SLNANDState *s; DriveInfo *nand; @@ -178,10 +166,8 @@ static int sl_nand_init(SysBusDevice *dev) { nand = drive_get(IF_MTD, 0, 0); s->nand = nand_init(nand ? nand->bdrv : NULL, s->manf_id, s->chip_id); - iomemtype = cpu_register_io_memory(sl_readfn, - sl_writefn, s, DEVICE_NATIVE_ENDIAN); - - sysbus_init_mmio(dev, 0x40, iomemtype); + memory_region_init_io(&s->iomem, &sl_ops, s, "sl", 0x40); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } @@ -898,6 +884,7 @@ static void spitz_common_init(ram_addr_t ram_size, PXA2xxState *cpu; DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *rom = g_new(MemoryRegion, 1); if (!cpu_model) cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; @@ -907,8 +894,9 @@ static void spitz_common_init(ram_addr_t ram_size, sl_flash_register(cpu, (model == spitz) ? FLASH_128M : FLASH_1024M); - cpu_register_physical_memory(0, SPITZ_ROM, - qemu_ram_alloc(NULL, "spitz.rom", SPITZ_ROM) | IO_MEM_ROM); + memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM); + memory_region_set_readonly(rom, true); + memory_region_add_subregion(address_space_mem, 0, rom); /* Setup peripherals */ spitz_keyboard_register(cpu); diff --git a/hw/strongarm.c b/hw/strongarm.c index 6097ea2c18..a3d908051f 100644 --- a/hw/strongarm.c +++ b/hw/strongarm.c @@ -68,6 +68,7 @@ static struct { /* Interrupt Controller */ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq irq; qemu_irq fiq; @@ -109,7 +110,8 @@ static void strongarm_pic_set_irq(void *opaque, int irq, int level) strongarm_pic_update(s); } -static uint32_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset) +static uint64_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset, + unsigned size) { StrongARMPICState *s = opaque; @@ -134,7 +136,7 @@ static uint32_t strongarm_pic_mem_read(void *opaque, target_phys_addr_t offset) } static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset, - uint32_t value) + uint64_t value, unsigned size) { StrongARMPICState *s = opaque; @@ -156,27 +158,19 @@ static void strongarm_pic_mem_write(void *opaque, target_phys_addr_t offset, strongarm_pic_update(s); } -static CPUReadMemoryFunc * const strongarm_pic_readfn[] = { - strongarm_pic_mem_read, - strongarm_pic_mem_read, - strongarm_pic_mem_read, -}; - -static CPUWriteMemoryFunc * const strongarm_pic_writefn[] = { - strongarm_pic_mem_write, - strongarm_pic_mem_write, - strongarm_pic_mem_write, +static const MemoryRegionOps strongarm_pic_ops = { + .read = strongarm_pic_mem_read, + .write = strongarm_pic_mem_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int strongarm_pic_initfn(SysBusDevice *dev) { StrongARMPICState *s = FROM_SYSBUS(StrongARMPICState, dev); - int iomemtype; qdev_init_gpio_in(&dev->qdev, strongarm_pic_set_irq, SA_PIC_SRCS); - iomemtype = cpu_register_io_memory(strongarm_pic_readfn, - strongarm_pic_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &strongarm_pic_ops, s, "pic", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); sysbus_init_irq(dev, &s->fiq); @@ -229,6 +223,7 @@ static SysBusDeviceInfo strongarm_pic_info = { typedef struct { SysBusDevice busdev; + MemoryRegion iomem; uint32_t rttr; uint32_t rtsr; uint32_t rtar; @@ -287,7 +282,8 @@ static inline void strongarm_rtc_hz_tick(void *opaque) strongarm_rtc_int_update(s); } -static uint32_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr) +static uint64_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr, + unsigned size) { StrongARMRTCState *s = opaque; @@ -309,7 +305,7 @@ static uint32_t strongarm_rtc_read(void *opaque, target_phys_addr_t addr) } static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { StrongARMRTCState *s = opaque; uint32_t old_rtsr; @@ -349,23 +345,16 @@ static void strongarm_rtc_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const strongarm_rtc_readfn[] = { - strongarm_rtc_read, - strongarm_rtc_read, - strongarm_rtc_read, -}; - -static CPUWriteMemoryFunc * const strongarm_rtc_writefn[] = { - strongarm_rtc_write, - strongarm_rtc_write, - strongarm_rtc_write, +static const MemoryRegionOps strongarm_rtc_ops = { + .read = strongarm_rtc_read, + .write = strongarm_rtc_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int strongarm_rtc_init(SysBusDevice *dev) { StrongARMRTCState *s = FROM_SYSBUS(StrongARMRTCState, dev); struct tm tm; - int iomemtype; s->rttr = 0x0; s->rtsr = 0; @@ -381,9 +370,8 @@ static int strongarm_rtc_init(SysBusDevice *dev) sysbus_init_irq(dev, &s->rtc_irq); sysbus_init_irq(dev, &s->rtc_hz_irq); - iomemtype = cpu_register_io_memory(strongarm_rtc_readfn, - strongarm_rtc_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x10000, iomemtype); + memory_region_init_io(&s->iomem, &strongarm_rtc_ops, s, "rtc", 0x10000); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } @@ -443,6 +431,7 @@ static SysBusDeviceInfo strongarm_rtc_sysbus_info = { typedef struct StrongARMGPIOInfo StrongARMGPIOInfo; struct StrongARMGPIOInfo { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq handler[28]; qemu_irq irqs[11]; qemu_irq irqX; @@ -507,7 +496,8 @@ static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s) s->prev_level = level; } -static uint32_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset) +static uint64_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset, + unsigned size) { StrongARMGPIOInfo *s = opaque; @@ -548,8 +538,8 @@ static uint32_t strongarm_gpio_read(void *opaque, target_phys_addr_t offset) return 0; } -static void strongarm_gpio_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void strongarm_gpio_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { StrongARMGPIOInfo *s = opaque; @@ -592,16 +582,10 @@ static void strongarm_gpio_write(void *opaque, } } -static CPUReadMemoryFunc * const strongarm_gpio_readfn[] = { - strongarm_gpio_read, - strongarm_gpio_read, - strongarm_gpio_read -}; - -static CPUWriteMemoryFunc * const strongarm_gpio_writefn[] = { - strongarm_gpio_write, - strongarm_gpio_write, - strongarm_gpio_write +static const MemoryRegionOps strongarm_gpio_ops = { + .read = strongarm_gpio_read, + .write = strongarm_gpio_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static DeviceState *strongarm_gpio_init(target_phys_addr_t base, @@ -623,7 +607,6 @@ static DeviceState *strongarm_gpio_init(target_phys_addr_t base, static int strongarm_gpio_initfn(SysBusDevice *dev) { - int iomemtype; StrongARMGPIOInfo *s; int i; @@ -632,10 +615,9 @@ static int strongarm_gpio_initfn(SysBusDevice *dev) qdev_init_gpio_in(&dev->qdev, strongarm_gpio_set, 28); qdev_init_gpio_out(&dev->qdev, s->handler, 28); - iomemtype = cpu_register_io_memory(strongarm_gpio_readfn, - strongarm_gpio_writefn, s, DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->iomem, &strongarm_gpio_ops, s, "gpio", 0x1000); - sysbus_init_mmio(dev, 0x1000, iomemtype); + sysbus_init_mmio_region(dev, &s->iomem); for (i = 0; i < 11; i++) { sysbus_init_irq(dev, &s->irqs[i]); } @@ -678,6 +660,7 @@ static SysBusDeviceInfo strongarm_gpio_info = { typedef struct StrongARMPPCInfo StrongARMPPCInfo; struct StrongARMPPCInfo { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq handler[28]; uint32_t ilevel; @@ -716,7 +699,8 @@ static void strongarm_ppc_handler_update(StrongARMPPCInfo *s) s->prev_level = level; } -static uint32_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset) +static uint64_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset, + unsigned size) { StrongARMPPCInfo *s = opaque; @@ -745,8 +729,8 @@ static uint32_t strongarm_ppc_read(void *opaque, target_phys_addr_t offset) return 0; } -static void strongarm_ppc_write(void *opaque, - target_phys_addr_t offset, uint32_t value) +static void strongarm_ppc_write(void *opaque, target_phys_addr_t offset, + uint64_t value, unsigned size) { StrongARMPPCInfo *s = opaque; @@ -778,21 +762,14 @@ static void strongarm_ppc_write(void *opaque, } } -static CPUReadMemoryFunc * const strongarm_ppc_readfn[] = { - strongarm_ppc_read, - strongarm_ppc_read, - strongarm_ppc_read -}; - -static CPUWriteMemoryFunc * const strongarm_ppc_writefn[] = { - strongarm_ppc_write, - strongarm_ppc_write, - strongarm_ppc_write +static const MemoryRegionOps strongarm_ppc_ops = { + .read = strongarm_ppc_read, + .write = strongarm_ppc_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int strongarm_ppc_init(SysBusDevice *dev) { - int iomemtype; StrongARMPPCInfo *s; s = FROM_SYSBUS(StrongARMPPCInfo, dev); @@ -800,10 +777,9 @@ static int strongarm_ppc_init(SysBusDevice *dev) qdev_init_gpio_in(&dev->qdev, strongarm_ppc_set, 22); qdev_init_gpio_out(&dev->qdev, s->handler, 22); - iomemtype = cpu_register_io_memory(strongarm_ppc_readfn, - strongarm_ppc_writefn, s, DEVICE_NATIVE_ENDIAN); + memory_region_init_io(&s->iomem, &strongarm_ppc_ops, s, "ppc", 0x1000); - sysbus_init_mmio(dev, 0x1000, iomemtype); + sysbus_init_mmio_region(dev, &s->iomem); return 0; } @@ -871,6 +847,7 @@ static SysBusDeviceInfo strongarm_ppc_info = { typedef struct { SysBusDevice busdev; + MemoryRegion iomem; CharDriverState *chr; qemu_irq irq; @@ -1079,7 +1056,8 @@ static void strongarm_uart_tx(void *opaque) strongarm_uart_update_int_status(s); } -static uint32_t strongarm_uart_read(void *opaque, target_phys_addr_t addr) +static uint64_t strongarm_uart_read(void *opaque, target_phys_addr_t addr, + unsigned size) { StrongARMUARTState *s = opaque; uint16_t ret; @@ -1121,7 +1099,7 @@ static uint32_t strongarm_uart_read(void *opaque, target_phys_addr_t addr) } static void strongarm_uart_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { StrongARMUARTState *s = opaque; @@ -1176,26 +1154,18 @@ static void strongarm_uart_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const strongarm_uart_readfn[] = { - strongarm_uart_read, - strongarm_uart_read, - strongarm_uart_read, -}; - -static CPUWriteMemoryFunc * const strongarm_uart_writefn[] = { - strongarm_uart_write, - strongarm_uart_write, - strongarm_uart_write, +static const MemoryRegionOps strongarm_uart_ops = { + .read = strongarm_uart_read, + .write = strongarm_uart_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int strongarm_uart_init(SysBusDevice *dev) { StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev); - int iomemtype; - iomemtype = cpu_register_io_memory(strongarm_uart_readfn, - strongarm_uart_writefn, s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x10000, iomemtype); + memory_region_init_io(&s->iomem, &strongarm_uart_ops, s, "uart", 0x10000); + sysbus_init_mmio_region(dev, &s->iomem); sysbus_init_irq(dev, &s->irq); s->rx_timeout_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_rx_to, s); @@ -1288,6 +1258,7 @@ static SysBusDeviceInfo strongarm_uart_info = { /* Synchronous Serial Ports */ typedef struct { SysBusDevice busdev; + MemoryRegion iomem; qemu_irq irq; SSIBus *bus; @@ -1355,7 +1326,8 @@ static void strongarm_ssp_fifo_update(StrongARMSSPState *s) strongarm_ssp_int_update(s); } -static uint32_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr) +static uint64_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr, + unsigned size) { StrongARMSSPState *s = opaque; uint32_t retval; @@ -1388,7 +1360,7 @@ static uint32_t strongarm_ssp_read(void *opaque, target_phys_addr_t addr) } static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { StrongARMSSPState *s = opaque; @@ -1397,7 +1369,7 @@ static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr, s->sscr[0] = value & 0xffbf; if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) { printf("%s: Wrong data size: %i bits\n", __func__, - SSCR0_DSS(value)); + (int)SSCR0_DSS(value)); } if (!(value & SSCR0_SSE)) { s->sssr = 0; @@ -1452,16 +1424,10 @@ static void strongarm_ssp_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const strongarm_ssp_readfn[] = { - strongarm_ssp_read, - strongarm_ssp_read, - strongarm_ssp_read, -}; - -static CPUWriteMemoryFunc * const strongarm_ssp_writefn[] = { - strongarm_ssp_write, - strongarm_ssp_write, - strongarm_ssp_write, +static const MemoryRegionOps strongarm_ssp_ops = { + .read = strongarm_ssp_read, + .write = strongarm_ssp_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static int strongarm_ssp_post_load(void *opaque, int version_id) @@ -1475,15 +1441,12 @@ static int strongarm_ssp_post_load(void *opaque, int version_id) static int strongarm_ssp_init(SysBusDevice *dev) { - int iomemtype; StrongARMSSPState *s = FROM_SYSBUS(StrongARMSSPState, dev); sysbus_init_irq(dev, &s->irq); - iomemtype = cpu_register_io_memory(strongarm_ssp_readfn, - strongarm_ssp_writefn, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, 0x1000, iomemtype); + memory_region_init_io(&s->iomem, &strongarm_ssp_ops, s, "ssp", 0x1000); + sysbus_init_mmio_region(dev, &s->iomem); s->bus = ssi_create_bus(&dev->qdev, "ssi"); return 0; @@ -1523,7 +1486,8 @@ static SysBusDeviceInfo strongarm_ssp_info = { }; /* Main CPU functions */ -StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev) +StrongARMState *sa1110_init(MemoryRegion *sysmem, + unsigned int sdram_size, const char *rev) { StrongARMState *s; qemu_irq *pic; @@ -1547,9 +1511,8 @@ StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev) exit(1); } - cpu_register_physical_memory(SA_SDCS0, - sdram_size, qemu_ram_alloc(NULL, "strongarm.sdram", - sdram_size) | IO_MEM_RAM); + memory_region_init_ram(&s->sdram, NULL, "strongarm.sdram", sdram_size); + memory_region_add_subregion(sysmem, SA_SDCS0, &s->sdram); pic = arm_pic_init_cpu(s->env); s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000, diff --git a/hw/strongarm.h b/hw/strongarm.h index a81b110e23..684f61bee3 100644 --- a/hw/strongarm.h +++ b/hw/strongarm.h @@ -1,6 +1,8 @@ #ifndef _STRONGARM_H #define _STRONGARM_H +#include "memory.h" + #define SA_CS0 0x00000000 #define SA_CS1 0x08000000 #define SA_CS2 0x10000000 @@ -52,6 +54,7 @@ enum { typedef struct { CPUState *env; + MemoryRegion sdram; DeviceState *pic; DeviceState *gpio; DeviceState *ppc; @@ -59,6 +62,7 @@ typedef struct { SSIBus *ssp_bus; } StrongARMState; -StrongARMState *sa1110_init(unsigned int sdram_size, const char *rev); +StrongARMState *sa1110_init(MemoryRegion *sysmem, + unsigned int sdram_size, const char *rev); #endif diff --git a/hw/sun4m.c b/hw/sun4m.c index 71bf648e69..314edc4d87 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -593,19 +593,25 @@ static void idreg_init(target_phys_addr_t addr) cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data)); } +typedef struct IDRegState { + SysBusDevice busdev; + MemoryRegion mem; +} IDRegState; + static int idreg_init1(SysBusDevice *dev) { - ram_addr_t idreg_offset; + IDRegState *s = FROM_SYSBUS(IDRegState, dev); - idreg_offset = qemu_ram_alloc(NULL, "sun4m.idreg", sizeof(idreg_data)); - sysbus_init_mmio(dev, sizeof(idreg_data), idreg_offset | IO_MEM_ROM); + memory_region_init_ram(&s->mem, NULL, "sun4m.idreg", sizeof(idreg_data)); + memory_region_set_readonly(&s->mem, true); + sysbus_init_mmio_region(dev, &s->mem); return 0; } static SysBusDeviceInfo idreg_info = { .init = idreg_init1, .qdev.name = "macio_idreg", - .qdev.size = sizeof(SysBusDevice), + .qdev.size = sizeof(IDRegState), }; static void idreg_register_devices(void) @@ -615,6 +621,11 @@ static void idreg_register_devices(void) device_init(idreg_register_devices); +typedef struct AFXState { + SysBusDevice busdev; + MemoryRegion mem; +} AFXState; + /* SS-5 TCX AFX register */ static void afx_init(target_phys_addr_t addr) { @@ -630,17 +641,17 @@ static void afx_init(target_phys_addr_t addr) static int afx_init1(SysBusDevice *dev) { - ram_addr_t afx_offset; + AFXState *s = FROM_SYSBUS(AFXState, dev); - afx_offset = qemu_ram_alloc(NULL, "sun4m.afx", 4); - sysbus_init_mmio(dev, 4, afx_offset | IO_MEM_RAM); + memory_region_init_ram(&s->mem, NULL, "sun4m.afx", 4); + sysbus_init_mmio_region(dev, &s->mem); return 0; } static SysBusDeviceInfo afx_info = { .init = afx_init1, .qdev.name = "tcx_afx", - .qdev.size = sizeof(SysBusDevice), + .qdev.size = sizeof(AFXState), }; static void afx_register_devices(void) @@ -650,6 +661,11 @@ static void afx_register_devices(void) device_init(afx_register_devices); +typedef struct PROMState { + SysBusDevice busdev; + MemoryRegion prom; +} PROMState; + /* Boot PROM (OpenBIOS) */ static uint64_t translate_prom_address(void *opaque, uint64_t addr) { @@ -693,17 +709,18 @@ static void prom_init(target_phys_addr_t addr, const char *bios_name) static int prom_init1(SysBusDevice *dev) { - ram_addr_t prom_offset; + PROMState *s = FROM_SYSBUS(PROMState, dev); - prom_offset = qemu_ram_alloc(NULL, "sun4m.prom", PROM_SIZE_MAX); - sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); + memory_region_init_ram(&s->prom, NULL, "sun4m.prom", PROM_SIZE_MAX); + memory_region_set_readonly(&s->prom, true); + sysbus_init_mmio_region(dev, &s->prom); return 0; } static SysBusDeviceInfo prom_info = { .init = prom_init1, .qdev.name = "openprom", - .qdev.size = sizeof(SysBusDevice), + .qdev.size = sizeof(PROMState), .qdev.props = (Property[]) { {/* end of property list */} } @@ -719,19 +736,17 @@ device_init(prom_register_devices); typedef struct RamDevice { SysBusDevice busdev; + MemoryRegion ram; uint64_t size; } RamDevice; /* System RAM */ static int ram_init1(SysBusDevice *dev) { - ram_addr_t RAM_size, ram_offset; RamDevice *d = FROM_SYSBUS(RamDevice, dev); - RAM_size = d->size; - - ram_offset = qemu_ram_alloc(NULL, "sun4m.ram", RAM_size); - sysbus_init_mmio(dev, RAM_size, ram_offset); + memory_region_init_ram(&d->ram, NULL, "sun4m.ram", d->size); + sysbus_init_mmio_region(dev, &d->ram); return 0; } diff --git a/hw/sun4u.c b/hw/sun4u.c index 96fc3d0488..eaaefe3c94 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -574,6 +574,11 @@ static void pci_ebus_register(void) device_init(pci_ebus_register); +typedef struct PROMState { + SysBusDevice busdev; + MemoryRegion prom; +} PROMState; + static uint64_t translate_prom_address(void *opaque, uint64_t addr) { target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque; @@ -617,17 +622,18 @@ static void prom_init(target_phys_addr_t addr, const char *bios_name) static int prom_init1(SysBusDevice *dev) { - ram_addr_t prom_offset; + PROMState *s = FROM_SYSBUS(PROMState, dev); - prom_offset = qemu_ram_alloc(NULL, "sun4u.prom", PROM_SIZE_MAX); - sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM); + memory_region_init_ram(&s->prom, NULL, "sun4u.prom", PROM_SIZE_MAX); + memory_region_set_readonly(&s->prom, true); + sysbus_init_mmio_region(dev, &s->prom); return 0; } static SysBusDeviceInfo prom_info = { .init = prom_init1, .qdev.name = "openprom", - .qdev.size = sizeof(SysBusDevice), + .qdev.size = sizeof(PROMState), .qdev.props = (Property[]) { {/* end of property list */} } @@ -644,19 +650,17 @@ device_init(prom_register_devices); typedef struct RamDevice { SysBusDevice busdev; + MemoryRegion ram; uint64_t size; } RamDevice; /* System RAM */ static int ram_init1(SysBusDevice *dev) { - ram_addr_t RAM_size, ram_offset; RamDevice *d = FROM_SYSBUS(RamDevice, dev); - RAM_size = d->size; - - ram_offset = qemu_ram_alloc(NULL, "sun4u.ram", RAM_size); - sysbus_init_mmio(dev, RAM_size, ram_offset); + memory_region_init_ram(&d->ram, NULL, "sun4u.ram", d->size); + sysbus_init_mmio_region(dev, &d->ram); return 0; } diff --git a/hw/syborg.c b/hw/syborg.c index bc200e48aa..248de54c4e 100644 --- a/hw/syborg.c +++ b/hw/syborg.c @@ -26,6 +26,7 @@ #include "boards.h" #include "arm-misc.h" #include "net.h" +#include "exec-memory.h" static struct arm_boot_info syborg_binfo; @@ -35,9 +36,10 @@ static void syborg_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { CPUState *env; + MemoryRegion *sysmem = get_system_memory(); + MemoryRegion *ram = g_new(MemoryRegion, 1); qemu_irq *cpu_pic; qemu_irq pic[64]; - ram_addr_t ram_addr; DeviceState *dev; int i; @@ -50,8 +52,8 @@ static void syborg_init(ram_addr_t ram_size, } /* RAM at address zero. */ - ram_addr = qemu_ram_alloc(NULL, "syborg.ram", ram_size); - cpu_register_physical_memory(0, ram_size, ram_addr | IO_MEM_RAM); + memory_region_init_ram(ram, NULL, "syborg.ram", ram_size); + memory_region_add_subregion(sysmem, 0, ram); cpu_pic = arm_pic_init_cpu(env); dev = sysbus_create_simple("syborg,interrupt", 0xC0000000, diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c index c28005a86b..c144dcf5ff 100644 --- a/hw/tc6393xb.c +++ b/hw/tc6393xb.c @@ -79,6 +79,7 @@ #define NAND_MODE_ECC_RST 0x60 struct TC6393xbState { + MemoryRegion iomem; qemu_irq irq; qemu_irq *sub_irqs; struct { @@ -122,7 +123,7 @@ struct TC6393xbState { ECCState ecc; DisplayState *ds; - ram_addr_t vram_addr; + MemoryRegion vram; uint16_t *vram_ptr; uint32_t scr_width, scr_height; /* in pixels */ qemu_irq l3v; @@ -495,7 +496,9 @@ static void tc6393xb_update_display(void *opaque) } -static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { +static uint64_t tc6393xb_readb(void *opaque, target_phys_addr_t addr, + unsigned size) +{ TC6393xbState *s = opaque; switch (addr >> 8) { @@ -516,7 +519,8 @@ static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) { return 0; } -static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) { +static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, + uint64_t value, unsigned size) { TC6393xbState *s = opaque; switch (addr >> 8) { @@ -532,51 +536,21 @@ static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t valu tc6393xb_nand_writeb(s, addr & 0xff, value); else fprintf(stderr, "tc6393xb: unhandled write at %08x: %02x\n", - (uint32_t) addr, value & 0xff); -} - -static uint32_t tc6393xb_readw(void *opaque, target_phys_addr_t addr) -{ - return (tc6393xb_readb(opaque, addr) & 0xff) | - (tc6393xb_readb(opaque, addr + 1) << 8); -} - -static uint32_t tc6393xb_readl(void *opaque, target_phys_addr_t addr) -{ - return (tc6393xb_readb(opaque, addr) & 0xff) | - ((tc6393xb_readb(opaque, addr + 1) & 0xff) << 8) | - ((tc6393xb_readb(opaque, addr + 2) & 0xff) << 16) | - ((tc6393xb_readb(opaque, addr + 3) & 0xff) << 24); + (uint32_t) addr, (int)value & 0xff); } -static void tc6393xb_writew(void *opaque, target_phys_addr_t addr, uint32_t value) +TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) { - tc6393xb_writeb(opaque, addr, value); - tc6393xb_writeb(opaque, addr + 1, value >> 8); -} - -static void tc6393xb_writel(void *opaque, target_phys_addr_t addr, uint32_t value) -{ - tc6393xb_writeb(opaque, addr, value); - tc6393xb_writeb(opaque, addr + 1, value >> 8); - tc6393xb_writeb(opaque, addr + 2, value >> 16); - tc6393xb_writeb(opaque, addr + 3, value >> 24); -} - -TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) -{ - int iomemtype; TC6393xbState *s; DriveInfo *nand; - CPUReadMemoryFunc * const tc6393xb_readfn[] = { - tc6393xb_readb, - tc6393xb_readw, - tc6393xb_readl, - }; - CPUWriteMemoryFunc * const tc6393xb_writefn[] = { - tc6393xb_writeb, - tc6393xb_writew, - tc6393xb_writel, + static const MemoryRegionOps tc6393xb_ops = { + .read = tc6393xb_readb, + .write = tc6393xb_writeb, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, }; s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState)); @@ -591,13 +565,12 @@ TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq) nand = drive_get(IF_MTD, 0, 0); s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76); - iomemtype = cpu_register_io_memory(tc6393xb_readfn, - tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x10000, iomemtype); + memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000); + memory_region_add_subregion(sysmem, base, &s->iomem); - s->vram_addr = qemu_ram_alloc(NULL, "tc6393xb.vram", 0x100000); - s->vram_ptr = qemu_get_ram_ptr(s->vram_addr); - cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr); + memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000); + s->vram_ptr = memory_region_get_ram_ptr(&s->vram); + memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); s->scr_width = 480; s->scr_height = 640; s->ds = graphic_console_init(tc6393xb_update_display, @@ -40,7 +40,15 @@ typedef struct TCXState { DisplayState *ds; uint8_t *vram; uint32_t *vram24, *cplane; - ram_addr_t vram_offset, vram24_offset, cplane_offset; + MemoryRegion vram_mem; + MemoryRegion vram_8bit; + MemoryRegion vram_24bit; + MemoryRegion vram_cplane; + MemoryRegion dac; + MemoryRegion tec; + MemoryRegion thc24; + MemoryRegion thc8; + ram_addr_t vram24_offset, cplane_offset; uint32_t vram_size; uint32_t palette[256]; uint8_t r[256], g[256], b[256]; @@ -56,7 +64,7 @@ static void tcx_set_dirty(TCXState *s) unsigned int i; for (i = 0; i < MAXX * MAXY; i += TARGET_PAGE_SIZE) { - cpu_physical_memory_set_dirty(s->vram_offset + i); + memory_region_set_dirty(&s->vram_mem, i); } } @@ -65,8 +73,8 @@ static void tcx24_set_dirty(TCXState *s) unsigned int i; for (i = 0; i < MAXX * MAXY * 4; i += TARGET_PAGE_SIZE) { - cpu_physical_memory_set_dirty(s->vram24_offset + i); - cpu_physical_memory_set_dirty(s->cplane_offset + i); + memory_region_set_dirty(&s->vram_mem, s->vram24_offset + i); + memory_region_set_dirty(&s->vram_mem, s->cplane_offset + i); } } @@ -174,16 +182,18 @@ static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d, } } -static inline int check_dirty(ram_addr_t page, ram_addr_t page24, +static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24, ram_addr_t cpage) { int ret; unsigned int off; - ret = cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG); + ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA); for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) { - ret |= cpu_physical_memory_get_dirty(page24 + off, VGA_DIRTY_FLAG); - ret |= cpu_physical_memory_get_dirty(cpage + off, VGA_DIRTY_FLAG); + ret |= memory_region_get_dirty(&s->vram_mem, page24 + off, + DIRTY_MEMORY_VGA); + ret |= memory_region_get_dirty(&s->vram_mem, cpage + off, + DIRTY_MEMORY_VGA); } return ret; } @@ -192,16 +202,17 @@ static inline void reset_dirty(TCXState *ts, ram_addr_t page_min, ram_addr_t page_max, ram_addr_t page24, ram_addr_t cpage) { - cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, - VGA_DIRTY_FLAG); - page_min -= ts->vram_offset; - page_max -= ts->vram_offset; - cpu_physical_memory_reset_dirty(page24 + page_min * 4, - page24 + page_max * 4 + TARGET_PAGE_SIZE, - VGA_DIRTY_FLAG); - cpu_physical_memory_reset_dirty(cpage + page_min * 4, - cpage + page_max * 4 + TARGET_PAGE_SIZE, - VGA_DIRTY_FLAG); + memory_region_reset_dirty(&ts->vram_mem, + page_min, page_max + TARGET_PAGE_SIZE, + DIRTY_MEMORY_VGA); + memory_region_reset_dirty(&ts->vram_mem, + page24 + page_min * 4, + page24 + page_max * 4 + TARGET_PAGE_SIZE, + DIRTY_MEMORY_VGA); + memory_region_reset_dirty(&ts->vram_mem, + cpage + page_min * 4, + cpage + page_max * 4 + TARGET_PAGE_SIZE, + DIRTY_MEMORY_VGA); } /* Fixed line length 1024 allows us to do nice tricks not possible on @@ -216,7 +227,7 @@ static void tcx_update_display(void *opaque) if (ds_get_bits_per_pixel(ts->ds) == 0) return; - page = ts->vram_offset; + page = 0; y_start = -1; page_min = -1; page_max = 0; @@ -242,7 +253,7 @@ static void tcx_update_display(void *opaque) } for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) { - if (cpu_physical_memory_get_dirty(page, VGA_DIRTY_FLAG)) { + if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) { if (y_start < 0) y_start = y; if (page < page_min) @@ -279,8 +290,9 @@ static void tcx_update_display(void *opaque) } /* reset modified pages */ if (page_max >= page_min) { - cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE, - VGA_DIRTY_FLAG); + memory_region_reset_dirty(&ts->vram_mem, + page_min, page_max + TARGET_PAGE_SIZE, + DIRTY_MEMORY_VGA); } } @@ -294,7 +306,7 @@ static void tcx24_update_display(void *opaque) if (ds_get_bits_per_pixel(ts->ds) != 32) return; - page = ts->vram_offset; + page = 0; page24 = ts->vram24_offset; cpage = ts->cplane_offset; y_start = -1; @@ -309,7 +321,7 @@ static void tcx24_update_display(void *opaque) for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE, page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) { - if (check_dirty(page, page24, cpage)) { + if (check_dirty(ts, page, page24, cpage)) { if (y_start < 0) y_start = y; if (page < page_min) @@ -421,18 +433,20 @@ static void tcx_reset(DeviceState *d) s->r[255] = s->g[255] = s->b[255] = 255; update_palette_entries(s, 0, 256); memset(s->vram, 0, MAXX*MAXY); - cpu_physical_memory_reset_dirty(s->vram_offset, s->vram_offset + - MAXX * MAXY * (1 + 4 + 4), VGA_DIRTY_FLAG); + memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4), + DIRTY_MEMORY_VGA); s->dac_index = 0; s->dac_state = 0; } -static uint32_t tcx_dac_readl(void *opaque, target_phys_addr_t addr) +static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr, + unsigned size) { return 0; } -static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) +static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val, + unsigned size) { TCXState *s = opaque; @@ -468,77 +482,77 @@ static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint32_t val) return; } -static CPUReadMemoryFunc * const tcx_dac_read[3] = { - NULL, - NULL, - tcx_dac_readl, +static const MemoryRegionOps tcx_dac_ops = { + .read = tcx_dac_readl, + .write = tcx_dac_writel, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; -static CPUWriteMemoryFunc * const tcx_dac_write[3] = { - NULL, - NULL, - tcx_dac_writel, -}; - -static uint32_t tcx_dummy_readl(void *opaque, target_phys_addr_t addr) +static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr, + unsigned size) { return 0; } -static void tcx_dummy_writel(void *opaque, target_phys_addr_t addr, - uint32_t val) +static void dummy_writel(void *opaque, target_phys_addr_t addr, + uint64_t val, unsigned size) { } -static CPUReadMemoryFunc * const tcx_dummy_read[3] = { - NULL, - NULL, - tcx_dummy_readl, -}; - -static CPUWriteMemoryFunc * const tcx_dummy_write[3] = { - NULL, - NULL, - tcx_dummy_writel, +static const MemoryRegionOps dummy_ops = { + .read = dummy_readl, + .write = dummy_writel, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, }; static int tcx_init1(SysBusDevice *dev) { TCXState *s = FROM_SYSBUS(TCXState, dev); - int io_memory, dummy_memory; - ram_addr_t vram_offset; + ram_addr_t vram_offset = 0; int size; uint8_t *vram_base; - vram_offset = qemu_ram_alloc(NULL, "tcx.vram", s->vram_size * (1 + 4 + 4)); - vram_base = qemu_get_ram_ptr(vram_offset); - s->vram_offset = vram_offset; + memory_region_init_ram(&s->vram_mem, NULL, "tcx.vram", + s->vram_size * (1 + 4 + 4)); + vram_base = memory_region_get_ram_ptr(&s->vram_mem); /* 8-bit plane */ s->vram = vram_base; size = s->vram_size; - sysbus_init_mmio(dev, size, s->vram_offset); + memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit", + &s->vram_mem, vram_offset, size); + sysbus_init_mmio_region(dev, &s->vram_8bit); vram_offset += size; vram_base += size; /* DAC */ - io_memory = cpu_register_io_memory(tcx_dac_read, tcx_dac_write, s, - DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, TCX_DAC_NREGS, io_memory); + memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS); + sysbus_init_mmio_region(dev, &s->dac); /* TEC (dummy) */ - dummy_memory = cpu_register_io_memory(tcx_dummy_read, tcx_dummy_write, - s, DEVICE_NATIVE_ENDIAN); - sysbus_init_mmio(dev, TCX_TEC_NREGS, dummy_memory); + memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS); + sysbus_init_mmio_region(dev, &s->tec); /* THC: NetBSD writes here even with 8-bit display: dummy */ - sysbus_init_mmio(dev, TCX_THC_NREGS_24, dummy_memory); + memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24", + TCX_THC_NREGS_24); + sysbus_init_mmio_region(dev, &s->thc24); if (s->depth == 24) { /* 24-bit plane */ size = s->vram_size * 4; s->vram24 = (uint32_t *)vram_base; s->vram24_offset = vram_offset; - sysbus_init_mmio(dev, size, vram_offset); + memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit", + &s->vram_mem, vram_offset, size); + sysbus_init_mmio_region(dev, &s->vram_24bit); vram_offset += size; vram_base += size; @@ -546,14 +560,18 @@ static int tcx_init1(SysBusDevice *dev) size = s->vram_size * 4; s->cplane = (uint32_t *)vram_base; s->cplane_offset = vram_offset; - sysbus_init_mmio(dev, size, vram_offset); + memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane", + &s->vram_mem, vram_offset, size); + sysbus_init_mmio_region(dev, &s->vram_cplane); s->ds = graphic_console_init(tcx24_update_display, tcx24_invalidate_display, tcx24_screen_dump, NULL, s); } else { /* THC 8 bit (dummy) */ - sysbus_init_mmio(dev, TCX_THC_NREGS_8, dummy_memory); + memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8", + TCX_THC_NREGS_8); + sysbus_init_mmio_region(dev, &s->thc8); s->ds = graphic_console_init(tcx_update_display, tcx_invalidate_display, @@ -220,7 +220,7 @@ static void tosa_init(ram_addr_t ram_size, cpu_register_physical_memory(0, TOSA_ROM, qemu_ram_alloc(NULL, "tosa.rom", TOSA_ROM) | IO_MEM_ROM); - tmio = tc6393xb_init(0x10000000, + tmio = tc6393xb_init(address_space_mem, 0x10000000, qdev_get_gpio_in(cpu->gpio, TOSA_GPIO_TC6393XB_INT)); scp0 = sysbus_create_simple("scoop", 0x08800000, NULL); |