diff options
| -rw-r--r-- | hw/pxa.h | 16 | ||||
| -rw-r--r-- | hw/pxa2xx.c | 45 | ||||
| -rw-r--r-- | hw/pxa2xx_dma.c | 186 | ||||
| -rw-r--r-- | hw/pxa2xx_mmci.c | 16 |
4 files changed, 152 insertions, 111 deletions
@@ -71,12 +71,8 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base, void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); /* pxa2xx_dma.c */ -typedef struct PXA2xxDMAState PXA2xxDMAState; -PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, - qemu_irq irq); -PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, - qemu_irq irq); -void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on); +DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq); +DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq); /* pxa2xx_lcd.c */ typedef struct PXA2xxLCDState PXA2xxLCDState; @@ -88,7 +84,8 @@ void pxa2xx_lcdc_oritentation(void *opaque, int angle); /* pxa2xx_mmci.c */ typedef struct PXA2xxMMCIState PXA2xxMMCIState; PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, - BlockDriverState *bd, qemu_irq irq, void *dma); + BlockDriverState *bd, qemu_irq irq, + qemu_irq rx_dma, qemu_irq tx_dma); void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, qemu_irq coverswitch); @@ -123,7 +120,7 @@ typedef struct { CPUState *env; DeviceState *pic; qemu_irq reset; - PXA2xxDMAState *dma; + DeviceState *dma; DeviceState *gpio; PXA2xxLCDState *lcd; SSIBus **ssp; @@ -181,7 +178,8 @@ typedef struct { struct PXA2xxI2SState { qemu_irq irq; - PXA2xxDMAState *dma; + qemu_irq rx_dma; + qemu_irq tx_dma; void (*data_req)(void *, int, int); uint32_t control[2]; diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index 7c31fab9f5..dfea01ad92 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -1585,8 +1585,8 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s) tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) && i2s->enable && !SACR_DPRL(i2s->control[1]); - pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs); - pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs); + qemu_set_irq(i2s->rx_dma, rfs); + qemu_set_irq(i2s->tx_dma, tfs); i2s->status &= 0xe0; if (i2s->fifo_len < 16 || !i2s->enable) @@ -1769,14 +1769,15 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx) } static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, - qemu_irq irq, PXA2xxDMAState *dma) + qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma) { int iomemtype; PXA2xxI2SState *s = (PXA2xxI2SState *) qemu_mallocz(sizeof(PXA2xxI2SState)); s->irq = irq; - s->dma = dma; + s->rx_dma = rx_dma; + s->tx_dma = tx_dma; s->data_req = pxa2xx_i2s_data_req; pxa2xx_i2s_reset(s); @@ -1794,7 +1795,8 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base, /* PXA Fast Infra-red Communications Port */ struct PXA2xxFIrState { qemu_irq irq; - PXA2xxDMAState *dma; + qemu_irq rx_dma; + qemu_irq tx_dma; int enable; CharDriverState *chr; @@ -1848,8 +1850,8 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s) (s->status[0] & (1 << 1)); /* TUR */ intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */ - pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1); - pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1); + qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1); + qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1); qemu_set_irq(s->irq, intr && s->enable); } @@ -2028,7 +2030,7 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id) } static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, - qemu_irq irq, PXA2xxDMAState *dma, + qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma, CharDriverState *chr) { int iomemtype; @@ -2036,7 +2038,8 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base, qemu_mallocz(sizeof(PXA2xxFIrState)); s->irq = irq; - s->dma = dma; + s->rx_dma = rx_dma; + s->tx_dma = tx_dma; s->chr = chr; pxa2xx_fir_reset(s); @@ -2116,7 +2119,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) exit(1); } s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv, - qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma); + qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), + qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), + qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); for (i = 0; pxa270_serial[i].io_base; i ++) if (serial_hds[i]) @@ -2134,7 +2139,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) if (serial_hds[i]) s->fir = pxa2xx_fir_init(0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), - s->dma, serial_hds[i]); + qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), + qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), + serial_hds[i]); s->lcd = pxa2xx_lcdc_init(0x44000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); @@ -2195,7 +2202,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision) qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); s->i2s = pxa2xx_i2s_init(0x40400000, - qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma); + qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), + qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), + qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); s->kp = pxa27x_keypad_init(0x41500000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD)); @@ -2250,7 +2259,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) exit(1); } s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv, - qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma); + qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), + qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI), + qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI)); for (i = 0; pxa255_serial[i].io_base; i ++) if (serial_hds[i]) { @@ -2269,7 +2280,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) if (serial_hds[i]) s->fir = pxa2xx_fir_init(0x40800000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP), - s->dma, serial_hds[i]); + qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP), + qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP), + serial_hds[i]); s->lcd = pxa2xx_lcdc_init(0x44000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD)); @@ -2330,7 +2343,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size) qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff); s->i2s = pxa2xx_i2s_init(0x40400000, - qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma); + qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), + qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S), + qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S)); /* GPIO1 resets the processor */ /* The handler can be overridden by board-specific code */ diff --git a/hw/pxa2xx_dma.c b/hw/pxa2xx_dma.c index 92c3e1ee20..6c599a0b07 100644 --- a/hw/pxa2xx_dma.c +++ b/hw/pxa2xx_dma.c @@ -10,6 +10,12 @@ #include "hw.h" #include "pxa.h" +#include "sysbus.h" + +#define PXA255_DMA_NUM_CHANNELS 16 +#define PXA27X_DMA_NUM_CHANNELS 32 + +#define PXA2XX_DMA_NUM_REQUESTS 75 typedef struct { target_phys_addr_t descr; @@ -20,7 +26,8 @@ typedef struct { int request; } PXA2xxDMAChannel; -struct PXA2xxDMAState { +typedef struct PXA2xxDMAState { + SysBusDevice busdev; qemu_irq irq; uint32_t stopintr; @@ -35,16 +42,11 @@ struct PXA2xxDMAState { int channels; PXA2xxDMAChannel *chan; - uint8_t *req; + uint8_t req[PXA2XX_DMA_NUM_REQUESTS]; /* Flag to avoid recursive DMA invocations. */ int running; -}; - -#define PXA255_DMA_NUM_CHANNELS 16 -#define PXA27X_DMA_NUM_CHANNELS 32 - -#define PXA2XX_DMA_NUM_REQUESTS 75 +} PXA2xxDMAState; #define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */ #define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */ @@ -424,73 +426,19 @@ static CPUWriteMemoryFunc * const pxa2xx_dma_writefn[] = { pxa2xx_dma_write }; -static void pxa2xx_dma_save(QEMUFile *f, void *opaque) -{ - PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; - int i; - - qemu_put_be32(f, s->channels); - - qemu_put_be32s(f, &s->stopintr); - qemu_put_be32s(f, &s->eorintr); - qemu_put_be32s(f, &s->rasintr); - qemu_put_be32s(f, &s->startintr); - qemu_put_be32s(f, &s->endintr); - qemu_put_be32s(f, &s->align); - qemu_put_be32s(f, &s->pio); - - qemu_put_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); - for (i = 0; i < s->channels; i ++) { - qemu_put_betl(f, s->chan[i].descr); - qemu_put_betl(f, s->chan[i].src); - qemu_put_betl(f, s->chan[i].dest); - qemu_put_be32s(f, &s->chan[i].cmd); - qemu_put_be32s(f, &s->chan[i].state); - qemu_put_be32(f, s->chan[i].request); - }; -} +static void pxa2xx_dma_request(void *opaque, int req_num, int on); -static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id) -{ - PXA2xxDMAState *s = (PXA2xxDMAState *) opaque; - int i; - - if (qemu_get_be32(f) != s->channels) - return -EINVAL; - - qemu_get_be32s(f, &s->stopintr); - qemu_get_be32s(f, &s->eorintr); - qemu_get_be32s(f, &s->rasintr); - qemu_get_be32s(f, &s->startintr); - qemu_get_be32s(f, &s->endintr); - qemu_get_be32s(f, &s->align); - qemu_get_be32s(f, &s->pio); - - qemu_get_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS); - for (i = 0; i < s->channels; i ++) { - s->chan[i].descr = qemu_get_betl(f); - s->chan[i].src = qemu_get_betl(f); - s->chan[i].dest = qemu_get_betl(f); - qemu_get_be32s(f, &s->chan[i].cmd); - qemu_get_be32s(f, &s->chan[i].state); - s->chan[i].request = qemu_get_be32(f); - }; - - return 0; -} - -static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, - qemu_irq irq, int channels) +static int pxa2xx_dma_init(SysBusDevice *dev) { int i, iomemtype; PXA2xxDMAState *s; - s = (PXA2xxDMAState *) - qemu_mallocz(sizeof(PXA2xxDMAState)); + s = FROM_SYSBUS(PXA2xxDMAState, dev); + + if (s->channels <= 0) { + return -1; + } - s->channels = channels; s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels); - s->irq = irq; - s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels); for (i = 0; i < s->channels; i ++) @@ -498,29 +446,47 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base, memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS); + qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS); + iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn, pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(base, 0x00010000, iomemtype); + sysbus_init_mmio(dev, 0x00010000, iomemtype); + sysbus_init_irq(dev, &s->irq); - register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s); - - return s; + return 0; } -PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base, - qemu_irq irq) +DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq) { - return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS); + DeviceState *dev; + + dev = qdev_create(NULL, "pxa2xx-dma"); + qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); + qdev_init_nofail(dev); + + sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); + sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); + + return dev; } -PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base, - qemu_irq irq) +DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq) { - return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS); + DeviceState *dev; + + dev = qdev_create(NULL, "pxa2xx-dma"); + qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS); + qdev_init_nofail(dev); + + sysbus_mmio_map(sysbus_from_qdev(dev), 0, base); + sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq); + + return dev; } -void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on) +static void pxa2xx_dma_request(void *opaque, int req_num, int on) { + PXA2xxDMAState *s = opaque; int ch; if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num); @@ -542,3 +508,63 @@ void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on) pxa2xx_dma_update(s, ch); } } + +static bool is_version_0(void *opaque, int version_id) +{ + return version_id == 0; +} + +static VMStateDescription vmstate_pxa2xx_dma_chan = { + .name = "pxa2xx_dma_chan", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(descr, PXA2xxDMAChannel), + VMSTATE_UINTTL(src, PXA2xxDMAChannel), + VMSTATE_UINTTL(dest, PXA2xxDMAChannel), + VMSTATE_UINT32(cmd, PXA2xxDMAChannel), + VMSTATE_UINT32(state, PXA2xxDMAChannel), + VMSTATE_INT32(request, PXA2xxDMAChannel), + VMSTATE_END_OF_LIST(), + }, +}; + +static VMStateDescription vmstate_pxa2xx_dma = { + .name = "pxa2xx_dma", + .version_id = 1, + .minimum_version_id = 0, + .minimum_version_id_old = 0, + .fields = (VMStateField[]) { + VMSTATE_UNUSED_TEST(is_version_0, 4), + VMSTATE_UINT32(stopintr, PXA2xxDMAState), + VMSTATE_UINT32(eorintr, PXA2xxDMAState), + VMSTATE_UINT32(rasintr, PXA2xxDMAState), + VMSTATE_UINT32(startintr, PXA2xxDMAState), + VMSTATE_UINT32(endintr, PXA2xxDMAState), + VMSTATE_UINT32(align, PXA2xxDMAState), + VMSTATE_UINT32(pio, PXA2xxDMAState), + VMSTATE_BUFFER(req, PXA2xxDMAState), + VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels, + vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel), + VMSTATE_END_OF_LIST(), + }, +}; + +static SysBusDeviceInfo pxa2xx_dma_info = { + .init = pxa2xx_dma_init, + .qdev.name = "pxa2xx-dma", + .qdev.desc = "PXA2xx DMA controller", + .qdev.size = sizeof(PXA2xxDMAState), + .qdev.vmsd = &vmstate_pxa2xx_dma, + .qdev.props = (Property[]) { + DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1), + DEFINE_PROP_END_OF_LIST(), + }, +}; + +static void pxa2xx_dma_register(void) +{ + sysbus_register_withprop(&pxa2xx_dma_info); +} +device_init(pxa2xx_dma_register); diff --git a/hw/pxa2xx_mmci.c b/hw/pxa2xx_mmci.c index 24d409d1a1..d86f735a2e 100644 --- a/hw/pxa2xx_mmci.c +++ b/hw/pxa2xx_mmci.c @@ -10,10 +10,12 @@ #include "hw.h" #include "pxa.h" #include "sd.h" +#include "qdev.h" struct PXA2xxMMCIState { qemu_irq irq; - void *dma; + qemu_irq rx_dma; + qemu_irq tx_dma; SDState *card; @@ -102,10 +104,8 @@ static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s) if (s->cmdat & CMDAT_DMA_EN) { mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ; - pxa2xx_dma_request(s->dma, - PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ)); - pxa2xx_dma_request(s->dma, - PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ)); + qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ)); + qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ)); } qemu_set_irq(s->irq, !!(s->intreq & ~mask)); @@ -518,14 +518,16 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id) } PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base, - BlockDriverState *bd, qemu_irq irq, void *dma) + BlockDriverState *bd, qemu_irq irq, + qemu_irq rx_dma, qemu_irq tx_dma) { int iomemtype; PXA2xxMMCIState *s; s = (PXA2xxMMCIState *) qemu_mallocz(sizeof(PXA2xxMMCIState)); s->irq = irq; - s->dma = dma; + s->rx_dma = rx_dma; + s->tx_dma = tx_dma; iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn, pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN); |