diff options
| -rw-r--r-- | hw/integratorcp.c | 10 | ||||
| -rw-r--r-- | hw/pl011.c | 4 | ||||
| -rw-r--r-- | hw/pl050.c | 4 | ||||
| -rw-r--r-- | hw/pl080.c | 4 | ||||
| -rw-r--r-- | hw/pl110.c | 4 | ||||
| -rw-r--r-- | hw/pl181.c | 4 | ||||
| -rw-r--r-- | hw/pl190.c | 4 | ||||
| -rw-r--r-- | hw/smc91c111.c | 4 |
8 files changed, 20 insertions, 18 deletions
diff --git a/hw/integratorcp.c b/hw/integratorcp.c index 0091f4fd18..75315a8b99 100644 --- a/hw/integratorcp.c +++ b/hw/integratorcp.c @@ -99,7 +99,7 @@ static uint32_t integratorcm_read(void *opaque, target_phys_addr_t offset) return 0; default: cpu_abort (cpu_single_env, - "integratorcm_read: Unimplemented offset 0x%x\n", offset); + "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset); return 0; } } @@ -207,7 +207,7 @@ static void integratorcm_write(void *opaque, target_phys_addr_t offset, break; default: cpu_abort (cpu_single_env, - "integratorcm_write: Unimplemented offset 0x%x\n", offset); + "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset); break; } } @@ -414,7 +414,8 @@ static uint32_t icp_control_read(void *opaque, target_phys_addr_t offset) case 3: /* CP_DECODE */ return 0x11; default: - cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n", + (int)offset); return 0; } } @@ -431,7 +432,8 @@ static void icp_control_write(void *opaque, target_phys_addr_t offset, /* Nothing interesting implemented yet. */ break; default: - cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n", + (int)offset); } } static CPUReadMemoryFunc *icp_control_readfn[] = { diff --git a/hw/pl011.c b/hw/pl011.c index 94ed6994d7..df3349188e 100644 --- a/hw/pl011.c +++ b/hw/pl011.c @@ -99,7 +99,7 @@ static uint32_t pl011_read(void *opaque, target_phys_addr_t offset) case 18: /* UARTDMACR */ return s->dmacr; default: - cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset); return 0; } } @@ -172,7 +172,7 @@ static void pl011_write(void *opaque, target_phys_addr_t offset, cpu_abort(cpu_single_env, "PL011: DMA not implemented\n"); break; default: - cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset); } } diff --git a/hw/pl050.c b/hw/pl050.c index b3a27976c8..1f56261b40 100644 --- a/hw/pl050.c +++ b/hw/pl050.c @@ -79,7 +79,7 @@ static uint32_t pl050_read(void *opaque, target_phys_addr_t offset) case 4: /* KMIIR */ return s->pending | 2; default: - cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl050_read: Bad offset %x\n", (int)offset); return 0; } } @@ -108,7 +108,7 @@ static void pl050_write(void *opaque, target_phys_addr_t offset, s->clk = value; return; default: - cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl050_write: Bad offset %x\n", (int)offset); } } static CPUReadMemoryFunc *pl050_readfn[] = { diff --git a/hw/pl080.c b/hw/pl080.c index b24cfbaf01..d581024ca8 100644 --- a/hw/pl080.c +++ b/hw/pl080.c @@ -243,7 +243,7 @@ static uint32_t pl080_read(void *opaque, target_phys_addr_t offset) return s->sync; default: bad_offset: - cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", offset); + cpu_abort(cpu_single_env, "pl080_read: Bad offset %x\n", (int)offset); return 0; } } @@ -305,7 +305,7 @@ static void pl080_write(void *opaque, target_phys_addr_t offset, break; default: bad_offset: - cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", offset); + cpu_abort(cpu_single_env, "pl080_write: Bad offset %x\n", (int)offset); } pl080_update(s); } diff --git a/hw/pl110.c b/hw/pl110.c index adaf1315fc..97cbee545a 100644 --- a/hw/pl110.c +++ b/hw/pl110.c @@ -326,7 +326,7 @@ static uint32_t pl110_read(void *opaque, target_phys_addr_t offset) case 12: /* LCDLPCURR */ return s->lpbase; default: - cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl110_read: Bad offset %x\n", (int)offset); return 0; } } @@ -393,7 +393,7 @@ static void pl110_write(void *opaque, target_phys_addr_t offset, pl110_update(s); break; default: - cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl110_write: Bad offset %x\n", (int)offset); } } diff --git a/hw/pl181.c b/hw/pl181.c index a905cbb210..bd067ddacc 100644 --- a/hw/pl181.c +++ b/hw/pl181.c @@ -333,7 +333,7 @@ static uint32_t pl181_read(void *opaque, target_phys_addr_t offset) return value; } default: - cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl181_read: Bad offset %x\n", (int)offset); return 0; } } @@ -405,7 +405,7 @@ static void pl181_write(void *opaque, target_phys_addr_t offset, } break; default: - cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl181_write: Bad offset %x\n", (int)offset); } pl181_update(s); } diff --git a/hw/pl190.c b/hw/pl190.c index 23494d8e10..79ba3ab790 100644 --- a/hw/pl190.c +++ b/hw/pl190.c @@ -139,7 +139,7 @@ static uint32_t pl190_read(void *opaque, target_phys_addr_t offset) case 13: /* DEFVECTADDR */ return s->vect_addr[16]; default: - cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", offset); + cpu_abort (cpu_single_env, "pl190_read: Bad offset %x\n", (int)offset); return 0; } } @@ -197,7 +197,7 @@ static void pl190_write(void *opaque, target_phys_addr_t offset, uint32_t val) cpu_abort(cpu_single_env, "pl190: Test mode not implemented\n"); break; default: - cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", offset); + cpu_abort(cpu_single_env, "pl190_write: Bad offset %x\n", (int)offset); return; } pl190_update(s); diff --git a/hw/smc91c111.c b/hw/smc91c111.c index b8d0cba5f2..25e6f79c71 100644 --- a/hw/smc91c111.c +++ b/hw/smc91c111.c @@ -413,7 +413,7 @@ static void smc91c111_writeb(void *opaque, target_phys_addr_t offset, break; } cpu_abort (cpu_single_env, "smc91c111_write: Bad reg %d:%x\n", - s->bank, offset); + s->bank, (int)offset); } static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) @@ -555,7 +555,7 @@ static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset) break; } cpu_abort (cpu_single_env, "smc91c111_read: Bad reg %d:%x\n", - s->bank, offset); + s->bank, (int)offset); return 0; } |