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authorPeter Maydell <peter.maydell@linaro.org>2018-05-29 13:01:11 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-05-29 13:01:11 +0100
commite609fa71e89c81fbe2670411be62da95dfb093e0 (patch)
treefc1b96d12b19dbe85aa270ecc56f9401b695ed99 /ui
parentdcd425608240ac6a5a223df2e8ce852b8fe1a661 (diff)
parentd10367e035eab12c77b83b5985915ff7f003de1f (diff)
Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream' into staging
Tag edgar/xilinx-next-2018-05-29-v1.for-upstream # gpg: Signature made Tue 29 May 2018 09:58:30 BST # gpg: using RSA key 29C596780F6BCA83 # gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" # gpg: aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" # Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF 4151 29C5 9678 0F6B CA83 * remotes/edgar/tags/edgar/xilinx-next-2018-05-29-v1.for-upstream: (38 commits) target-microblaze: Consolidate MMU enabled checks target-microblaze: cpu_mmu_index: Fixup indentation target-microblaze: Use tcg_gen_movcond in eval_cond_jmp target-microblaze: Convert env_btarget to i64 target-microblaze: Remove argument b in eval_cc() target-microblaze: Use table based condition-codes conversion target-microblaze: mmu: Cleanup debug log messages target-microblaze: Simplify address computation using tcg_gen_addi_i32() target-microblaze: Allow address sizes between 32 and 64 bits target-microblaze: Add support for extended access to TLBLO target-microblaze: dec_msr: Plug a temp leak target-microblaze: mmu: Add a configurable output address mask target-microblaze: mmu: Prepare for 64-bit addresses target-microblaze: mmu: Remove unused register state target-microblaze: mmu: Add R_TBLX_MISS macros target-microblaze: Implement MFSE EAR target-microblaze: Add Extended Addressing target-microblaze: Setup for 64bit addressing target-microblaze: Make special registers 64-bit target-microblaze: dec_msr: Fix MTS to FSR ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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