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| author | Max Filippov <jcmvbkbc@gmail.com> | 2016-11-11 22:40:18 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2017-01-15 13:01:56 -0800 |
| commit | 9e03ade4411c81a7f7d974dcedf0390835ce4096 (patch) | |
| tree | 5ed7163044ac610d041277e20def7990e507b1b5 /tests/tcg | |
| parent | 4b37aaa879d508494df14bdc49830cdf8aa77a57 (diff) | |
target/xtensa: implement MEMCTL SR
MEMCTL SR controls zero overhead loop buffer and number of ways enabled
in L1 caches.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'tests/tcg')
0 files changed, 0 insertions, 0 deletions