diff options
| author | Jin Guojie <jinguojie@loongson.cn> | 2017-01-05 12:57:54 +0800 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-06 10:03:54 -0800 |
| commit | 999b941633cabf2487d9bc77ce382b3fde3cd66d (patch) | |
| tree | 448c72982b8e8a42de6162484d57823e45bbd245 /tcg | |
| parent | 98d690761a97da268fa279e544c86c88683a304f (diff) | |
tcg-mips: Adjust calling conventions for mips64
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: James Hogan <james.hogan@imgtec.com>
Tested-by: YunQiang Su <wzssyqa@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Jin Guojie <jinguojie@loongson.cn>
Message-Id: <1483592275-4496-10-git-send-email-jinguojie@loongson.cn>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/mips/tcg-target.h | 19 | ||||
| -rw-r--r-- | tcg/mips/tcg-target.inc.c | 21 |
2 files changed, 30 insertions, 10 deletions
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 4b7d3ae80a..d352c97389 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -27,7 +27,14 @@ #ifndef MIPS_TCG_TARGET_H #define MIPS_TCG_TARGET_H -#define TCG_TARGET_REG_BITS 32 +#if _MIPS_SIM == _ABIO32 +# define TCG_TARGET_REG_BITS 32 +#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 +# define TCG_TARGET_REG_BITS 64 +#else +# error "Unknown ABI" +#endif + #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 @@ -71,9 +78,13 @@ typedef enum { } TCGReg; /* used for function call generation */ -#define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_STACK_OFFSET 16 -#define TCG_TARGET_CALL_ALIGN_ARGS 1 +#define TCG_TARGET_STACK_ALIGN 16 +#if _MIPS_SIM == _ABIO32 +# define TCG_TARGET_CALL_STACK_OFFSET 16 +#else +# define TCG_TARGET_CALL_STACK_OFFSET 0 +#endif +#define TCG_TARGET_CALL_ALIGN_ARGS 1 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index b7e2586db8..7282a4afb1 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -91,10 +91,6 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_S8, /* Call clobbered registers. */ - TCG_REG_T0, - TCG_REG_T1, - TCG_REG_T2, - TCG_REG_T3, TCG_REG_T4, TCG_REG_T5, TCG_REG_T6, @@ -105,17 +101,27 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_V0, /* Argument registers, opposite order of allocation. */ + TCG_REG_T3, + TCG_REG_T2, + TCG_REG_T1, + TCG_REG_T0, TCG_REG_A3, TCG_REG_A2, TCG_REG_A1, TCG_REG_A0, }; -static const TCGReg tcg_target_call_iarg_regs[4] = { +static const TCGReg tcg_target_call_iarg_regs[] = { TCG_REG_A0, TCG_REG_A1, TCG_REG_A2, - TCG_REG_A3 + TCG_REG_A3, +#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, +#endif }; static const TCGReg tcg_target_call_oarg_regs[2] = { @@ -2427,6 +2433,9 @@ static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff); + if (TCG_TARGET_REG_BITS == 64) { + tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff); + } tcg_regset_set(tcg_target_call_clobber_regs, (1 << TCG_REG_V0) | (1 << TCG_REG_V1) | |