diff options
| author | Claudio Fontana <claudio.fontana@huawei.com> | 2013-06-12 16:20:23 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2013-06-12 16:20:23 +0100 |
| commit | 9c4a059df3501ba53c00724287ef50bba80b5f80 (patch) | |
| tree | 80fc6bb16b7452de204255aa01482314442b7261 /tcg | |
| parent | 7deea126b24508e8ffa7aa4aecfa6fa97eddc384 (diff) | |
tcg/aarch64: implement byte swap operations
implement the optional byte swap operations with the dedicated
aarch64 instructions.
Signed-off-by: Claudio Fontana <claudio.fontana@huawei.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 51AC9A33.9050003@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/aarch64/tcg-target.c | 32 | ||||
| -rw-r--r-- | tcg/aarch64/tcg-target.h | 10 |
2 files changed, 37 insertions, 5 deletions
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bb59794046..ba65a62516 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -660,6 +660,20 @@ static inline void tcg_out_goto_label_cond(TCGContext *s, } } +static inline void tcg_out_rev(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ + /* using REV 0x5ac00800 */ + unsigned int base = ext ? 0xdac00c00 : 0x5ac00800; + tcg_out32(s, base | rm << 5 | rd); +} + +static inline void tcg_out_rev16(TCGContext *s, int ext, TCGReg rd, TCGReg rm) +{ + /* using REV16 0x5ac00400 */ + unsigned int base = ext ? 0xdac00400 : 0x5ac00400; + tcg_out32(s, base | rm << 5 | rd); +} + #ifdef CONFIG_SOFTMMU #include "exec/softmmu_defs.h" @@ -1012,6 +1026,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_qemu_st(s, args, 3); break; + case INDEX_op_bswap64_i64: + ext = 1; /* fall through */ + case INDEX_op_bswap32_i64: + case INDEX_op_bswap32_i32: + tcg_out_rev(s, ext, args[0], args[1]); + break; + case INDEX_op_bswap16_i64: + case INDEX_op_bswap16_i32: + tcg_out_rev16(s, 0, args[0], args[1]); + break; + default: tcg_abort(); /* opcode not implemented */ } @@ -1093,6 +1118,13 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_qemu_st16, { "l", "l" } }, { INDEX_op_qemu_st32, { "l", "l" } }, { INDEX_op_qemu_st64, { "l", "l" } }, + + { INDEX_op_bswap16_i32, { "r", "r" } }, + { INDEX_op_bswap32_i32, { "r", "r" } }, + { INDEX_op_bswap16_i64, { "r", "r" } }, + { INDEX_op_bswap32_i64, { "r", "r" } }, + { INDEX_op_bswap64_i64, { "r", "r" } }, + { -1 }, }; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 075ab2afde..247ef4385d 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -44,8 +44,8 @@ typedef enum { #define TCG_TARGET_HAS_ext16s_i32 0 #define TCG_TARGET_HAS_ext8u_i32 0 #define TCG_TARGET_HAS_ext16u_i32 0 -#define TCG_TARGET_HAS_bswap16_i32 0 -#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_bswap16_i32 1 +#define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_not_i32 0 #define TCG_TARGET_HAS_neg_i32 0 #define TCG_TARGET_HAS_rot_i32 1 @@ -68,9 +68,9 @@ typedef enum { #define TCG_TARGET_HAS_ext8u_i64 0 #define TCG_TARGET_HAS_ext16u_i64 0 #define TCG_TARGET_HAS_ext32u_i64 0 -#define TCG_TARGET_HAS_bswap16_i64 0 -#define TCG_TARGET_HAS_bswap32_i64 0 -#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_bswap16_i64 1 +#define TCG_TARGET_HAS_bswap32_i64 1 +#define TCG_TARGET_HAS_bswap64_i64 1 #define TCG_TARGET_HAS_not_i64 0 #define TCG_TARGET_HAS_neg_i64 0 #define TCG_TARGET_HAS_rot_i64 1 |