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authorRichard Henderson <rth@twiddle.net>2013-03-26 16:50:29 -0400
committerRichard Henderson <rth@twiddle.net>2013-04-05 13:35:40 -0500
commit36017dc68aa8c345d10ad7ba7bc3dba580f3f035 (patch)
treec0034c92f9a0607b06e5dba7803ae80c99460ec9 /tcg
parent3790b9180a070eab619438dc0fd83de33ec8cbbd (diff)
tcg-s390: Implement mulu2_i64 opcode
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
-rw-r--r--tcg/s390/tcg-target.c5
-rw-r--r--tcg/s390/tcg-target.h2
2 files changed, 6 insertions, 1 deletions
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index b00776371d..81e2f6ab4c 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -147,6 +147,7 @@ typedef enum S390Opcode {
RRE_LRVR = 0xb91f,
RRE_LRVGR = 0xb90f,
RRE_LTGR = 0xb902,
+ RRE_MLGR = 0xb986,
RRE_MSGR = 0xb90c,
RRE_MSR = 0xb252,
RRE_NGR = 0xb980,
@@ -1981,6 +1982,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_divu2_i64:
tcg_out_insn(s, RRE, DLGR, TCG_REG_R2, args[4]);
break;
+ case INDEX_op_mulu2_i64:
+ tcg_out_insn(s, RRE, MLGR, TCG_REG_R2, args[3]);
+ break;
case INDEX_op_shl_i64:
op = RSY_SLLG;
@@ -2156,6 +2160,7 @@ static const TCGTargetOpDef s390_op_defs[] = {
{ INDEX_op_div2_i64, { "b", "a", "0", "1", "r" } },
{ INDEX_op_divu2_i64, { "b", "a", "0", "1", "r" } },
+ { INDEX_op_mulu2_i64, { "b", "a", "0", "r" } },
{ INDEX_op_and_i64, { "r", "0", "rA" } },
{ INDEX_op_or_i64, { "r", "0", "rO" } },
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
index da726bd5fd..c0cb7141e7 100644
--- a/tcg/s390/tcg-target.h
+++ b/tcg/s390/tcg-target.h
@@ -92,7 +92,7 @@ typedef enum TCGReg {
#define TCG_TARGET_HAS_movcond_i64 0
#define TCG_TARGET_HAS_add2_i64 1
#define TCG_TARGET_HAS_sub2_i64 1
-#define TCG_TARGET_HAS_mulu2_i64 0
+#define TCG_TARGET_HAS_mulu2_i64 1
#define TCG_TARGET_HAS_muls2_i64 0
/* used for function call generation */