diff options
| author | Richard Henderson <rth@twiddle.net> | 2014-08-06 12:32:40 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@redhat.com> | 2014-09-29 14:55:27 -0400 |
| commit | de8301e542325fbc8accafbd8a3b50ae2554503e (patch) | |
| tree | a773c4018ec8a344a4e481bcd475ac554f8c751b /tcg | |
| parent | c470b663f71ccbaa90006acb797a847c290329f9 (diff) | |
tcg-sparc: Use UMULXHI instruction
Signed-off-by: Richard Henderson <rth@twiddle.net>
Diffstat (limited to 'tcg')
| -rw-r--r-- | tcg/sparc/tcg-target.c | 5 | ||||
| -rw-r--r-- | tcg/sparc/tcg-target.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index 0a8c26af63..0c4b028580 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -210,6 +210,7 @@ static const int tcg_target_call_oarg_regs[] = { #define ARITH_MOVR (INSN_OP(2) | INSN_OP3(0x2f)) #define ARITH_ADDXC (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x11)) +#define ARITH_UMULXHI (INSN_OP(2) | INSN_OP3(0x36) | INSN_OPF(0x16)) #define SHIFT_SLL (INSN_OP(2) | INSN_OP3(0x25)) #define SHIFT_SRL (INSN_OP(2) | INSN_OP3(0x26)) @@ -1435,6 +1436,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_addsub2_i64(s, args[0], args[1], args[2], args[3], args[4], const_args[4], args[5], const_args[5], true); break; + case INDEX_op_muluh_i64: + tcg_out_arith(s, args[0], args[1], args[2], ARITH_UMULXHI); + break; gen_arith: tcg_out_arithc(s, a0, a1, a2, c2, c); @@ -1535,6 +1539,7 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_add2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, { INDEX_op_sub2_i64, { "R", "R", "RZ", "RZ", "RJ", "RI" } }, + { INDEX_op_muluh_i64, { "R", "RZ", "RZ" } }, { INDEX_op_qemu_ld_i32, { "r", "A" } }, { INDEX_op_qemu_ld_i64, { "R", "A" } }, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 099b3080bf..0c4c8af0b2 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -143,7 +143,7 @@ extern bool use_vis3_instructions; #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i64 0 +#define TCG_TARGET_HAS_muluh_i64 use_vis3_instructions #define TCG_TARGET_HAS_mulsh_i64 0 #define TCG_AREG0 TCG_REG_I0 |