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authorRichard Henderson <richard.henderson@linaro.org>2021-07-26 10:32:17 -1000
committerRichard Henderson <richard.henderson@linaro.org>2021-10-05 16:53:17 -0700
commit4b473e0c60d802bb69accab3177d350fc580e2a4 (patch)
tree69d8dd81da9146b4048100c81f9e61deeee9d45c /tcg/tcg-op.c
parentc433e298d99228e41a78d480a505cfcc8c9ea067 (diff)
tcg: Expand MO_SIZE to 3 bits
We have lacked expressive support for memory sizes larger than 64-bits for a while. Fixing that requires adjustment to several points where we used this for array indexing, and two places that develop -Wswitch warnings after the change. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/tcg-op.c')
-rw-r--r--tcg/tcg-op.c13
1 files changed, 8 insertions, 5 deletions
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index c754396575..e01f68f44d 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -2780,10 +2780,13 @@ static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st)
}
break;
case MO_64:
- if (!is64) {
- tcg_abort();
+ if (is64) {
+ op &= ~MO_SIGN;
+ break;
}
- break;
+ /* fall through */
+ default:
+ g_assert_not_reached();
}
if (st) {
op &= ~MO_SIGN;
@@ -3095,7 +3098,7 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv,
# define WITH_ATOMIC64(X)
#endif
-static void * const table_cmpxchg[16] = {
+static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = {
[MO_8] = gen_helper_atomic_cmpxchgb,
[MO_16 | MO_LE] = gen_helper_atomic_cmpxchgw_le,
[MO_16 | MO_BE] = gen_helper_atomic_cmpxchgw_be,
@@ -3297,7 +3300,7 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGv addr, TCGv_i64 val,
}
#define GEN_ATOMIC_HELPER(NAME, OP, NEW) \
-static void * const table_##NAME[16] = { \
+static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] = { \
[MO_8] = gen_helper_atomic_##NAME##b, \
[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le, \
[MO_16 | MO_BE] = gen_helper_atomic_##NAME##w_be, \