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authorRichard Henderson <richard.henderson@linaro.org>2019-03-22 13:52:09 -0700
committerRichard Henderson <richard.henderson@linaro.org>2019-06-10 07:03:34 -0700
commita40ec84ee2b02086e27fab78a152c20b09c723cf (patch)
treecf5efed68e90ae2240ecf558eddb0e18d890e275 /tcg/i386
parent74433bf083b0766aba81534f92de13194f23ff3e (diff)
tcg: Create struct CPUTLB
Move all softmmu tlb data into this structure. Arrange the members so that we are able to place mask+table together and at a smaller absolute offset from ENV. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/i386')
-rw-r--r--tcg/i386/tcg-target.inc.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index c0443da4af..5f5b886c04 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -1730,10 +1730,10 @@ static inline void tcg_out_tlb_load(TCGContext *s, TCGReg addrlo, TCGReg addrhi,
TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS);
tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, r0, TCG_AREG0,
- offsetof(CPUArchState, tlb_mask[mem_index]));
+ offsetof(CPUArchState, tlb_.f[mem_index].mask));
tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, r0, TCG_AREG0,
- offsetof(CPUArchState, tlb_table[mem_index]));
+ offsetof(CPUArchState, tlb_.f[mem_index].table));
/* If the required alignment is at least as large as the access, simply
copy the address and mask. For lesser alignments, check that we don't