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authorRichard Henderson <richard.henderson@linaro.org>2021-05-03 16:47:52 -0700
committerRichard Henderson <richard.henderson@linaro.org>2021-06-04 11:50:11 -0700
commit000cf4777aadda69d14a6994ca0d195a36733cbd (patch)
treea01d2bbc4dbf2ac318f9754d18b2ae05d8c14a2f /tcg/arm/tcg-target.opc.h
parenta4fbbd779a29b912299bc2830f0157513080ddb7 (diff)
tcg/arm: Add host vector framework
Add registers and function stubs. The functionality is disabled via use_neon_instructions defined to 0. We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'tcg/arm/tcg-target.opc.h')
-rw-r--r--tcg/arm/tcg-target.opc.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/tcg/arm/tcg-target.opc.h b/tcg/arm/tcg-target.opc.h
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index 0000000000..7a4578e9b4
--- /dev/null
+++ b/tcg/arm/tcg-target.opc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2019 Linaro
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or
+ * (at your option) any later version.
+ *
+ * See the COPYING file in the top-level directory for details.
+ *
+ * Target-specific opcodes for host vector expansion. These will be
+ * emitted by tcg_expand_vec_op. For those familiar with GCC internals,
+ * consider these to be UNSPEC with names.
+ */