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authorRichard Henderson <richard.henderson@linaro.org>2020-02-07 14:04:26 +0000
committerPeter Maydell <peter.maydell@linaro.org>2020-02-07 14:04:26 +0000
commitd1b31428fd522b725bc053c84b5fbc8764061363 (patch)
tree2abff52870b0445fc81fe89c665e1605c07db5b9 /target
parent85d0dc9fa205027554372367f6925749a2d2b4c4 (diff)
target/arm: Update arm_phys_excp_target_el for TGE
The TGE bit routes all asynchronous exceptions to EL2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200206105448.4726-33-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/helper.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3b7b459314..56a62b11d0 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8446,6 +8446,12 @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
break;
};
+ /*
+ * For these purposes, TGE and AMO/IMO/FMO both force the
+ * interrupt to EL2. Fold TGE into the bit extracted above.
+ */
+ hcr |= (hcr_el2 & HCR_TGE) != 0;
+
/* Perform a table-lookup for the target EL given the current state */
target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];