aboutsummaryrefslogtreecommitdiff
path: root/target
diff options
context:
space:
mode:
authorAndrew Jones <drjones@redhat.com>2019-03-25 14:16:47 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-03-25 14:16:47 +0000
commita46118fc16537a593119e5b316052a98514046bb (patch)
tree36ecb48e61cbb0f79b1684647dfe3f587b95db54 /target
parentcbbb3041fe2f57a475cef5d6b0ef836118aad106 (diff)
target/arm: cortex-a7 and cortex-a15 have pmus
cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise them in ID_DFR0. Let's allow them to function. This also enables the pmu cpu property to work with these cpu types, i.e. we can now do '-cpu cortex-a15,pmu=off' to remove the pmu. Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190322162333.17159-3-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/cpu.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 96f0ff0ec7..504a4771fb 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1109,6 +1109,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
#endif
} else {
cpu->id_aa64dfr0 &= ~0xf00;
+ cpu->id_dfr0 &= ~(0xf << 24);
cpu->pmceid0 = 0;
cpu->pmceid1 = 0;
}
@@ -1744,6 +1745,7 @@ static void cortex_a7_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
cpu->midr = 0x410fc075;
cpu->reset_fpsid = 0x41023075;
@@ -1789,6 +1791,7 @@ static void cortex_a15_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
set_feature(&cpu->env, ARM_FEATURE_EL2);
set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
cpu->midr = 0x412fc0f1;
cpu->reset_fpsid = 0x410430f0;