diff options
| author | Bin Meng <bin.meng@windriver.com> | 2020-06-10 18:08:47 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-06-19 08:24:07 -0700 |
| commit | 4c56793f59b9a1513868e11fd87c5d6e4a5e8edd (patch) | |
| tree | 4e1266d25fe334d331ec4a234e3f7f884273d852 /target | |
| parent | e7b5dfd34f296db56aa5de31d1cf64dbe82674a3 (diff) | |
riscv: Generalize CPU init routine for the gcsu CPU
There is no need to have two functions that have almost the same
codes for 32-bit and 64-bit gcsu CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1591837729-27486-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target')
| -rw-r--r-- | target/riscv/cpu.c | 20 |
1 files changed, 6 insertions, 14 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 81cdea8680..437e141ef2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -134,16 +134,16 @@ static void riscv_base_cpu_init(Object *obj) set_resetvec(env, DEFAULT_RSTVEC); } -#if defined(TARGET_RISCV32) - -static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) +static void rvxx_gcsu_priv1_10_0_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); set_resetvec(env, DEFAULT_RSTVEC); } +#if defined(TARGET_RISCV32) + static void rv32imcu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -173,14 +173,6 @@ static void rv32imafcu_nommu_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) -static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; - set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, DEFAULT_RSTVEC); -} - static void rv64imacu_nommu_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -599,11 +591,11 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_gcsu_priv1_10_0_cpu_init), #elif defined(TARGET_RISCV64) DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), - DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_gcsu_priv1_10_0_cpu_init), #endif }; |