diff options
| author | Idan Horowitz <idan.horowitz@gmail.com> | 2022-04-01 15:35:49 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2022-04-01 15:35:49 +0100 |
| commit | bcd7a8cf38b7e9769f741419bc56675cbddb42c6 (patch) | |
| tree | f82f8210b4f8b5ccc89712dfef72554d7fa39f00 /target | |
| parent | d3b2d191119ee3e6364e470b9579e6353d202e54 (diff) | |
target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the
initial PA space used for stage 2 table walks is assigned based on the SW
and NSW bits of the VSTCR and VTCR registers.
This was already implemented for the recursive stage 2 page table walks
in S1_ptw_translate(), but was missing for the final stage 2 walk.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220327093427.1548629-3-idan.horowitz@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target')
| -rw-r--r-- | target/arm/helper.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c index a65b39625d..6fd5c27340 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12657,6 +12657,16 @@ bool get_phys_addr(CPUARMState *env, target_ulong address, return ret; } + if (arm_is_secure_below_el3(env)) { + if (attrs->secure) { + attrs->secure = !(env->cp15.vstcr_el2.raw_tcr & VSTCR_SW); + } else { + attrs->secure = !(env->cp15.vtcr_el2.raw_tcr & VTCR_NSW); + } + } else { + assert(!attrs->secure); + } + s2_mmu_idx = attrs->secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2; is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0; |