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authorPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-04-18 16:25:49 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-05-02 16:49:35 +0200
commitc284201702386b159277422318e51697647a2047 (patch)
tree25a6ee59c188ca1975e9b6d474c1ae15475dab6f /target
parentad520a978447bca03374b71e90d948826e669603 (diff)
target/mips: Restrict mmu_init() to TCG
mmu_init() is only required by TCG accelerator. Restrict its declaration and call to TCG. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-21-f4bug@amsat.org>
Diffstat (limited to 'target')
-rw-r--r--target/mips/cpu.c2
-rw-r--r--target/mips/internal.h3
-rw-r--r--target/mips/tcg/tcg-internal.h2
3 files changed, 3 insertions, 4 deletions
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index a751c95832..c3159e3d7f 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -708,7 +708,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
env->exception_base = (int32_t)0xBFC00000;
-#ifndef CONFIG_USER_ONLY
+#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY)
mmu_init(env, env->cpu_model);
#endif
fpu_init(env, env->cpu_model);
diff --git a/target/mips/internal.h b/target/mips/internal.h
index 6bac8ef704..2c9666905d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -233,9 +233,6 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value);
void cpu_mips_start_count(CPUMIPSState *env);
void cpu_mips_stop_count(CPUMIPSState *env);
-/* helper.c */
-void mmu_init(CPUMIPSState *env, const mips_def_t *def);
-
static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value)
{
env->active_tc.PC = value & ~(target_ulong)1;
diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h
index b65580af21..70655bab45 100644
--- a/target/mips/tcg/tcg-internal.h
+++ b/target/mips/tcg/tcg-internal.h
@@ -20,6 +20,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
#if !defined(CONFIG_USER_ONLY)
+void mmu_init(CPUMIPSState *env, const mips_def_t *def);
+
void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask);
uint32_t cpu_mips_get_random(CPUMIPSState *env);