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authorRichard Henderson <richard.henderson@linaro.org>2022-04-28 01:10:55 -0700
committerRichard Henderson <richard.henderson@linaro.org>2022-06-28 04:35:07 +0530
commited3a06b10a6abb53589d794ed23accf21be05633 (patch)
tree78e7bb0e6c8432afd1e985f3e8a156402f2821df /target
parent4cfeff4ac16bf5e3e1df44d5561b83e3bd3aab6c (diff)
semihosting: Return void from do_common_semihosting
Perform the cleanup in the FIXME comment in common_semi_gdb_syscall. Do not modify guest registers until the syscall is complete, which in the gdbstub case is asynchronous. In the synchronous non-gdbstub case, use common_semi_set_ret to set the result. Merge set_swi_errno into common_semi_cb. Rely on the latter for combined return value / errno setting. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target')
-rw-r--r--target/arm/helper.c4
-rw-r--r--target/arm/m_helper.c2
-rw-r--r--target/riscv/cpu_helper.c2
3 files changed, 4 insertions, 4 deletions
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2886a123a..f6dcb1a115 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10515,13 +10515,13 @@ static void handle_semihosting(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"...handling as semihosting call 0x%" PRIx64 "\n",
env->xregs[0]);
- env->xregs[0] = do_common_semihosting(cs);
+ do_common_semihosting(cs);
env->pc += 4;
} else {
qemu_log_mask(CPU_LOG_INT,
"...handling as semihosting call 0x%x\n",
env->regs[0]);
- env->regs[0] = do_common_semihosting(cs);
+ do_common_semihosting(cs);
env->regs[15] += env->thumb ? 2 : 4;
}
}
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
index a740c3e160..308610f6b4 100644
--- a/target/arm/m_helper.c
+++ b/target/arm/m_helper.c
@@ -2373,7 +2373,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
"...handling as semihosting call 0x%x\n",
env->regs[0]);
#ifdef CONFIG_TCG
- env->regs[0] = do_common_semihosting(cs);
+ do_common_semihosting(cs);
#else
g_assert_not_reached();
#endif
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 4a6700c890..be28615e23 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1347,7 +1347,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (cause == RISCV_EXCP_SEMIHOST) {
if (env->priv >= PRV_S) {
- env->gpr[xA0] = do_common_semihosting(cs);
+ do_common_semihosting(cs);
env->pc += 4;
return;
}