diff options
| author | Stefan Hajnoczi <stefanha@redhat.com> | 2023-08-24 09:17:05 -0400 |
|---|---|---|
| committer | Stefan Hajnoczi <stefanha@redhat.com> | 2023-08-24 09:17:05 -0400 |
| commit | 6030ef9d416d740eed9c0beaf7eef83d27eaf4eb (patch) | |
| tree | 18bb2d7fc4bf79934885d8dad843c1164ed80504 /target | |
| parent | 92e1d39f989771f9fc190234111863c7376487c5 (diff) | |
| parent | 3f6bec4a9f7c159d32d49f6df5c2c3d587b953b9 (diff) | |
Merge tag 'pull-loongarch-20230824' of https://gitlab.com/gaosong/qemu into staging
pull-loongarch-20230824
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#
# iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCZOcdAwAKCRBAov/yOSY+
# 3w3CA/sH8+Ay+Qnaqa2vEyuhOlFQuxHKeR7mYfsitAdzh8yMK2K8C2iBUzDzL1H3
# kZmZbCcYX7ko9RLhsuXmvfBJ7iwzY55ozSHLIjJ/VS4JVE5B0cUSZ5jjIPDqpzDs
# 7TUt9qpTkwg0e+klzVREWLSWP5xopvkRvFHZM3KZZhGMphOTUQ==
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# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 24 Aug 2023 05:04:03 EDT
# gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF
# gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20230824' of https://gitlab.com/gaosong/qemu: (31 commits)
hw/loongarch: Fix ACPI processor id off-by-one error
target/loongarch: Split fcc register to fcc0-7 in gdbstub
hw/intc/loongarch_pch: fix edge triggered irq handling
target/loongarch: cpu: Implement get_arch_id callback
target/loongarch: Add avail_IOCSR to check iocsr instructions
target/loongarch: Add avail_LSX to check LSX instructions
target/loongarch: Add avail_LAM to check atomic instructions
target/loongarch: Add avail_LSPW to check LSPW instructions
target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions
hw/loongarch: Remove restriction of la464 cores in the virt machine
target/loongarch: Add LoongArch32 cpu la132
target/loongarch: Add avail_64 to check la64-only instructions
target/loongarch: Add a check parameter to the TRANS macro
target/loongarch: Sign extend results in VA32 mode
target/loongarch: Truncate high 32 bits of address in VA32 mode
target/loongarch: Extract set_pc() helper
target/loongarch: Extract make_address_pc() helper
target/loongarch: Extract make_address_i() helper
target/loongarch: Extract make_address_x() helper
target/loongarch: Add LA64 & VA32 to DisasContext
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Diffstat (limited to 'target')
22 files changed, 1528 insertions, 1084 deletions
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index f8f24032cb..c59d7a9fcb 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6) FIELD(CSR_TLBIDX, NE, 31, 1) #define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */ -FIELD(CSR_TLBEHI, VPPN, 13, 35) +FIELD(CSR_TLBEHI_32, VPPN, 13, 19) +FIELD(CSR_TLBEHI_64, VPPN, 13, 35) #define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */ #define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */ @@ -66,10 +67,11 @@ FIELD(TLBENTRY, D, 1, 1) FIELD(TLBENTRY, PLV, 2, 2) FIELD(TLBENTRY, MAT, 4, 2) FIELD(TLBENTRY, G, 6, 1) -FIELD(TLBENTRY, PPN, 12, 36) -FIELD(TLBENTRY, NR, 61, 1) -FIELD(TLBENTRY, NX, 62, 1) -FIELD(TLBENTRY, RPLV, 63, 1) +FIELD(TLBENTRY_32, PPN, 8, 24) +FIELD(TLBENTRY_64, PPN, 12, 36) +FIELD(TLBENTRY_64, NR, 61, 1) +FIELD(TLBENTRY_64, NX, 62, 1) +FIELD(TLBENTRY_64, RPLV, 63, 1) #define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */ FIELD(CSR_ASID, ASID, 0, 10) @@ -163,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62) #define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */ #define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */ FIELD(CSR_TLBREHI, PS, 0, 6) -FIELD(CSR_TLBREHI, VPPN, 13, 35) +FIELD(CSR_TLBREHI_32, VPPN, 13, 19) +FIELD(CSR_TLBREHI_64, VPPN, 13, 35) #define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */ FIELD(CSR_TLBRPRMD, PPLV, 0, 2) FIELD(CSR_TLBRPRMD, PIE, 2, 1) @@ -187,10 +190,9 @@ FIELD(CSR_DMW, PLV1, 1, 1) FIELD(CSR_DMW, PLV2, 2, 1) FIELD(CSR_DMW, PLV3, 3, 1) FIELD(CSR_DMW, MAT, 4, 2) -FIELD(CSR_DMW, VSEG, 60, 4) - -#define dmw_va2pa(va) \ - (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS)) +FIELD(CSR_DMW_32, PSEG, 25, 3) +FIELD(CSR_DMW_32, VSEG, 29, 3) +FIELD(CSR_DMW_64, VSEG, 60, 4) /* Debug CSRs */ #define LOONGARCH_CSR_DBG 0x500 /* debug config */ diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index ad93ecac92..27fc6e1f33 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -81,7 +81,7 @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value) LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; - env->pc = value; + set_pc(env, value); } static vaddr loongarch_cpu_get_pc(CPUState *cs) @@ -168,7 +168,7 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) set_DERA: env->CSR_DERA = env->pc; env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1); - env->pc = env->CSR_EENTRY + 0x480; + set_pc(env, env->CSR_EENTRY + 0x480); break; case EXCCODE_INT: if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { @@ -249,7 +249,8 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) /* Find the highest-priority interrupt. */ vector = 31 - clz32(pending); - env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size; + set_pc(env, env->CSR_EENTRY + \ + (EXCCODE_EXTERNAL_INT + vector) * vec_size); qemu_log_mask(CPU_LOG_INT, "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx " cause %d\n" " A " TARGET_FMT_lx " D " @@ -260,10 +261,9 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) env->CSR_ECFG, env->CSR_ESTAT); } else { if (tlbfill) { - env->pc = env->CSR_TLBRENTRY; + set_pc(env, env->CSR_TLBRENTRY); } else { - env->pc = env->CSR_EENTRY; - env->pc += EXCODE_MCODE(cause) * vec_size; + set_pc(env, env->CSR_EENTRY + EXCODE_MCODE(cause) * vec_size); } qemu_log_mask(CPU_LOG_INT, "%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx @@ -324,7 +324,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs, CPULoongArchState *env = &cpu->env; tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); - env->pc = tb->pc; + set_pc(env, tb->pc); } static void loongarch_restore_state_to_opc(CPUState *cs, @@ -334,7 +334,7 @@ static void loongarch_restore_state_to_opc(CPUState *cs, LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; - env->pc = data[0]; + set_pc(env, data[0]); } #endif /* CONFIG_TCG */ @@ -391,6 +391,7 @@ static void loongarch_la464_initfn(Object *obj) data = FIELD_DP32(data, CPUCFG2, LSX, 1), data = FIELD_DP32(data, CPUCFG2, LLFTP, 1); data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1); + data = FIELD_DP32(data, CPUCFG2, LSPW, 1); data = FIELD_DP32(data, CPUCFG2, LAM, 1); env->cpucfg[2] = data; @@ -439,6 +440,35 @@ static void loongarch_la464_initfn(Object *obj) env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa); } +static void loongarch_la132_initfn(Object *obj) +{ + LoongArchCPU *cpu = LOONGARCH_CPU(obj); + CPULoongArchState *env = &cpu->env; + + int i; + + for (i = 0; i < 21; i++) { + env->cpucfg[i] = 0x0; + } + + cpu->dtb_compatible = "loongarch,Loongson-1C103"; + env->cpucfg[0] = 0x148042; /* PRID */ + + uint32_t data = 0; + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */ + data = FIELD_DP32(data, CPUCFG1, PGMMU, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR, 1); + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */ + data = FIELD_DP32(data, CPUCFG1, UAL, 1); + data = FIELD_DP32(data, CPUCFG1, RI, 0); + data = FIELD_DP32(data, CPUCFG1, EP, 0); + data = FIELD_DP32(data, CPUCFG1, RPLV, 0); + data = FIELD_DP32(data, CPUCFG1, HP, 1); + data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1); + env->cpucfg[1] = data; +} + static void loongarch_cpu_list_entry(gpointer data, gpointer user_data) { const char *typename = object_class_get_name(OBJECT_CLASS(data)); @@ -544,6 +574,8 @@ static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp) static void loongarch_qemu_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { + qemu_log_mask(LOG_UNIMP, "[%s]: Unimplemented reg 0x%" HWADDR_PRIx "\n", + __func__, addr); } static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) @@ -690,12 +722,14 @@ static struct TCGCPUOps loongarch_tcg_ops = { static const struct SysemuCPUOps loongarch_sysemu_ops = { .get_phys_page_debug = loongarch_cpu_get_phys_page_debug, }; -#endif -static gchar *loongarch_gdb_arch_name(CPUState *cs) +static int64_t loongarch_cpu_get_arch_id(CPUState *cs) { - return g_strdup("loongarch64"); + LoongArchCPU *cpu = LOONGARCH_CPU(cs); + + return cpu->phy_id; } +#endif static void loongarch_cpu_class_init(ObjectClass *c, void *data) { @@ -715,26 +749,51 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data) cc->set_pc = loongarch_cpu_set_pc; cc->get_pc = loongarch_cpu_get_pc; #ifndef CONFIG_USER_ONLY + cc->get_arch_id = loongarch_cpu_get_arch_id; dc->vmsd = &vmstate_loongarch_cpu; cc->sysemu_ops = &loongarch_sysemu_ops; #endif cc->disas_set_info = loongarch_cpu_disas_set_info; cc->gdb_read_register = loongarch_cpu_gdb_read_register; cc->gdb_write_register = loongarch_cpu_gdb_write_register; - cc->disas_set_info = loongarch_cpu_disas_set_info; - cc->gdb_num_core_regs = 35; - cc->gdb_core_xml_file = "loongarch-base64.xml"; cc->gdb_stop_before_watchpoint = true; - cc->gdb_arch_name = loongarch_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_ops = &loongarch_tcg_ops; #endif } -#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \ +static gchar *loongarch32_gdb_arch_name(CPUState *cs) +{ + return g_strdup("loongarch32"); +} + +static void loongarch32_cpu_class_init(ObjectClass *c, void *data) +{ + CPUClass *cc = CPU_CLASS(c); + + cc->gdb_num_core_regs = 35; + cc->gdb_core_xml_file = "loongarch-base32.xml"; + cc->gdb_arch_name = loongarch32_gdb_arch_name; +} + +static gchar *loongarch64_gdb_arch_name(CPUState *cs) +{ + return g_strdup("loongarch64"); +} + +static void loongarch64_cpu_class_init(ObjectClass *c, void *data) +{ + CPUClass *cc = CPU_CLASS(c); + + cc->gdb_num_core_regs = 35; + cc->gdb_core_xml_file = "loongarch-base64.xml"; + cc->gdb_arch_name = loongarch64_gdb_arch_name; +} + +#define DEFINE_LOONGARCH_CPU_TYPE(size, model, initfn) \ { \ - .parent = TYPE_LOONGARCH_CPU, \ + .parent = TYPE_LOONGARCH##size##_CPU, \ .instance_init = initfn, \ .name = LOONGARCH_CPU_TYPE_NAME(model), \ } @@ -750,7 +809,22 @@ static const TypeInfo loongarch_cpu_type_infos[] = { .class_size = sizeof(LoongArchCPUClass), .class_init = loongarch_cpu_class_init, }, - DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn), + { + .name = TYPE_LOONGARCH32_CPU, + .parent = TYPE_LOONGARCH_CPU, + + .abstract = true, + .class_init = loongarch32_cpu_class_init, + }, + { + .name = TYPE_LOONGARCH64_CPU, + .parent = TYPE_LOONGARCH_CPU, + + .abstract = true, + .class_init = loongarch64_cpu_class_init, + }, + DEFINE_LOONGARCH_CPU_TYPE(64, "la464", loongarch_la464_initfn), + DEFINE_LOONGARCH_CPU_TYPE(32, "la132", loongarch_la132_initfn), }; DEFINE_TYPES(loongarch_cpu_type_infos) diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index fa371ca8ba..4d7201995a 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -132,6 +132,11 @@ FIELD(CPUCFG1, HP, 24, 1) FIELD(CPUCFG1, IOCSR_BRD, 25, 1) FIELD(CPUCFG1, MSG_INT, 26, 1) +/* cpucfg[1].arch */ +#define CPUCFG1_ARCH_LA32R 0 +#define CPUCFG1_ARCH_LA32 1 +#define CPUCFG1_ARCH_LA64 2 + /* cpucfg[2] bits */ FIELD(CPUCFG2, FP, 0, 1) FIELD(CPUCFG2, FP_SP, 1, 1) @@ -371,12 +376,15 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPULoongArchState env; QEMUTimer timer; + uint32_t phy_id; /* 'compatible' string for this CPU for Linux device trees */ const char *dtb_compatible; }; #define TYPE_LOONGARCH_CPU "loongarch-cpu" +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu" +#define TYPE_LOONGARCH64_CPU "loongarch64-cpu" OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass, LOONGARCH_CPU) @@ -420,6 +428,31 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #endif } +static inline bool is_la64(CPULoongArchState *env) +{ + return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64; +} + +static inline bool is_va32(CPULoongArchState *env) +{ + /* VA32 if !LA64 or VA32L[1-3] */ + bool va32 = !is_la64(env); + uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); + if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { + va32 = true; + } + return va32; +} + +static inline void set_pc(CPULoongArchState *env, uint64_t value) +{ + if (is_va32(env)) { + env->pc = (uint32_t)value; + } else { + env->pc = value; + } +} + /* * LoongArch CPUs hardware flags. */ @@ -427,6 +460,7 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch) #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */ #define HW_FLAGS_EUEN_FPE 0x04 #define HW_FLAGS_EUEN_SXE 0x08 +#define HW_FLAGS_VA32 0x20 static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, uint64_t *cs_base, uint32_t *flags) @@ -436,6 +470,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc, *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK); *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE; *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE; + *flags |= is_va32(env) * HW_FLAGS_VA32; } void loongarch_cpu_list(void); diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index 0752fff924..b09804b62f 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; + uint64_t val; if (0 <= n && n < 32) { - return gdb_get_regl(mem_buf, env->gpr[n]); + val = env->gpr[n]; } else if (n == 32) { /* orig_a0 */ - return gdb_get_regl(mem_buf, 0); + val = 0; } else if (n == 33) { - return gdb_get_regl(mem_buf, env->pc); + val = env->pc; } else if (n == 34) { - return gdb_get_regl(mem_buf, env->CSR_BADV); + val = env->CSR_BADV; + } + + if (0 <= n && n <= 34) { + if (is_la64(env)) { + return gdb_get_reg64(mem_buf, val); + } else { + return gdb_get_reg32(mem_buf, val); + } } return 0; } @@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) { LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; - target_ulong tmp = ldtul_p(mem_buf); + target_ulong tmp; + int read_length; int length = 0; + if (is_la64(env)) { + tmp = ldq_p(mem_buf); + read_length = 8; + } else { + tmp = ldl_p(mem_buf); + read_length = 4; + } + if (0 <= n && n < 32) { env->gpr[n] = tmp; - length = sizeof(target_ulong); + length = read_length; } else if (n == 33) { - env->pc = tmp; - length = sizeof(target_ulong); + set_pc(env, tmp); + length = read_length; } return length; } @@ -70,10 +88,9 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env, { if (0 <= n && n < 32) { return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0)); - } else if (n == 32) { - uint64_t val = read_fcc(env); - return gdb_get_reg64(mem_buf, val); - } else if (n == 33) { + } else if (32 <= n && n < 40) { + return gdb_get_reg8(mem_buf, env->cf[n - 32]); + } else if (n == 40) { return gdb_get_reg32(mem_buf, env->fcsr0); } return 0; @@ -87,11 +104,10 @@ static int loongarch_gdb_set_fpu(CPULoongArchState *env, if (0 <= n && n < 32) { env->fpr[n].vreg.D(0) = ldq_p(mem_buf); length = 8; - } else if (n == 32) { - uint64_t val = ldq_p(mem_buf); - write_fcc(env, val); - length = 8; - } else if (n == 33) { + } else if (32 <= n && n < 40) { + env->cf[n - 32] = ldub_p(mem_buf); + length = 1; + } else if (n == 40) { env->fcsr0 = ldl_p(mem_buf); length = 4; } diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc index 43d6cf261d..2be057e932 100644 --- a/target/loongarch/insn_trans/trans_arith.c.inc +++ b/target/loongarch/insn_trans/trans_arith.c.inc @@ -72,7 +72,7 @@ static bool gen_pc(DisasContext *ctx, arg_r_i *a, target_ulong (*func)(target_ulong, int)) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); - target_ulong addr = func(ctx->base.pc_next, a->imm); + target_ulong addr = make_address_pc(ctx, func(ctx->base.pc_next, a->imm)); tcg_gen_movi_tl(dest, addr); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -199,6 +199,10 @@ static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a) TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE); TCGv src2 = tcg_constant_tl(a->imm); + if (!avail_64(ctx)) { + return false; + } + tcg_gen_deposit_tl(dest, src1, src2, 32, 32); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -211,6 +215,10 @@ static bool trans_lu52i_d(DisasContext *ctx, arg_lu52i_d *a) TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = tcg_constant_tl(a->imm); + if (!avail_64(ctx)) { + return false; + } + tcg_gen_deposit_tl(dest, src1, src2, 52, 12); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -242,51 +250,55 @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + if (!avail_64(ctx)) { + return false; + } + tcg_gen_addi_tl(dest, src1, a->imm << 16); gen_set_gpr(a->rd, dest, EXT_NONE); return true; } -TRANS(add_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl) -TRANS(add_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl) -TRANS(sub_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl) -TRANS(sub_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl) -TRANS(and, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl) -TRANS(or, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl) -TRANS(xor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl) -TRANS(nor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl) -TRANS(andn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl) -TRANS(orn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl) -TRANS(slt, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt) -TRANS(sltu, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu) -TRANS(mul_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl) -TRANS(mul_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl) -TRANS(mulh_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w) -TRANS(mulh_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w) -TRANS(mulh_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d) -TRANS(mulh_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du) -TRANS(mulw_d_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl) -TRANS(mulw_d_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl) -TRANS(div_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w) -TRANS(mod_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w) -TRANS(div_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du) -TRANS(mod_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du) -TRANS(div_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d) -TRANS(mod_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d) -TRANS(div_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du) -TRANS(mod_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du) -TRANS(slti, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt) -TRANS(sltui, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu) -TRANS(addi_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl) -TRANS(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl) -TRANS(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl) -TRANS(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl) -TRANS(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl) -TRANS(pcaddi, gen_pc, gen_pcaddi) -TRANS(pcalau12i, gen_pc, gen_pcalau12i) -TRANS(pcaddu12i, gen_pc, gen_pcaddu12i) -TRANS(pcaddu18i, gen_pc, gen_pcaddu18i) -TRANS(andi, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl) -TRANS(ori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl) -TRANS(xori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl) +TRANS(add_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl) +TRANS(add_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl) +TRANS(sub_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl) +TRANS(sub_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl) +TRANS(and, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl) +TRANS(or, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl) +TRANS(xor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl) +TRANS(nor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_nor_tl) +TRANS(andn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_andc_tl) +TRANS(orn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl) +TRANS(slt, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt) +TRANS(sltu, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu) +TRANS(mul_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl) +TRANS(mul_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl) +TRANS(mulh_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w) +TRANS(mulh_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w) +TRANS(mulh_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d) +TRANS(mulh_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du) +TRANS(mulw_d_w, 64, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl) +TRANS(mulw_d_wu, 64, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl) +TRANS(div_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w) +TRANS(mod_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w) +TRANS(div_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du) +TRANS(mod_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du) +TRANS(div_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d) +TRANS(mod_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d) +TRANS(div_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du) +TRANS(mod_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du) +TRANS(slti, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt) +TRANS(sltui, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu) +TRANS(addi_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl) +TRANS(addi_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl) +TRANS(alsl_w, ALL, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl) +TRANS(alsl_wu, 64, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl) +TRANS(alsl_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl) +TRANS(pcaddi, ALL, gen_pc, gen_pcaddi) +TRANS(pcalau12i, ALL, gen_pc, gen_pcalau12i) +TRANS(pcaddu12i, ALL, gen_pc, gen_pcaddu12i) +TRANS(pcaddu18i, 64, gen_pc, gen_pcaddu18i) +TRANS(andi, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl) +TRANS(ori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl) +TRANS(xori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl) diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc index 612709f2a7..40085190f6 100644 --- a/target/loongarch/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/insn_trans/trans_atomic.c.inc @@ -7,9 +7,8 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); - TCGv t0 = tcg_temp_new(); + TCGv t0 = make_address_i(ctx, src1, a->imm); - tcg_gen_addi_tl(t0, src1, a->imm); tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop); tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr)); tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval)); @@ -62,49 +61,51 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a, return false; } + addr = make_address_i(ctx, addr, 0); + func(dest, addr, val, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); return true; } -TRANS(ll_w, gen_ll, MO_TESL) -TRANS(sc_w, gen_sc, MO_TESL) -TRANS(ll_d, gen_ll, MO_TEUQ) -TRANS(sc_d, gen_sc, MO_TEUQ) -TRANS(amswap_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) -TRANS(amswap_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) -TRANS(amadd_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) -TRANS(amadd_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) -TRANS(amand_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) -TRANS(amand_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) -TRANS(amor_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) -TRANS(amor_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) -TRANS(amxor_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) -TRANS(amxor_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) -TRANS(ammax_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) -TRANS(ammax_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) -TRANS(ammin_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) -TRANS(ammin_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) -TRANS(ammax_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) -TRANS(ammax_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) -TRANS(ammin_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) -TRANS(ammin_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) -TRANS(amswap_db_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) -TRANS(amswap_db_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) -TRANS(amadd_db_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) -TRANS(amadd_db_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) -TRANS(amand_db_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) -TRANS(amand_db_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) -TRANS(amor_db_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) -TRANS(amor_db_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) -TRANS(amxor_db_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) -TRANS(amxor_db_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) -TRANS(ammax_db_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) -TRANS(ammax_db_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) -TRANS(ammin_db_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) -TRANS(ammin_db_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) -TRANS(ammax_db_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) -TRANS(ammax_db_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) -TRANS(ammin_db_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) -TRANS(ammin_db_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) +TRANS(ll_w, ALL, gen_ll, MO_TESL) +TRANS(sc_w, ALL, gen_sc, MO_TESL) +TRANS(ll_d, 64, gen_ll, MO_TEUQ) +TRANS(sc_d, 64, gen_sc, MO_TEUQ) +TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) +TRANS(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) +TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) +TRANS(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) +TRANS(amand_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) +TRANS(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) +TRANS(amor_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) +TRANS(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) +TRANS(amxor_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) +TRANS(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) +TRANS(ammax_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) +TRANS(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) +TRANS(ammin_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) +TRANS(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) +TRANS(ammax_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) +TRANS(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) +TRANS(ammin_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) +TRANS(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) +TRANS(amswap_db_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) +TRANS(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) +TRANS(amadd_db_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) +TRANS(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) +TRANS(amand_db_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) +TRANS(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) +TRANS(amor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) +TRANS(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) +TRANS(amxor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) +TRANS(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) +TRANS(ammax_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) +TRANS(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) +TRANS(ammin_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) +TRANS(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) +TRANS(ammax_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) +TRANS(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) +TRANS(ammin_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) +TRANS(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc index 25b4d7858b..ee5fa003ce 100644 --- a/target/loongarch/insn_trans/trans_bit.c.inc +++ b/target/loongarch/insn_trans/trans_bit.c.inc @@ -178,31 +178,31 @@ static void gen_masknez(TCGv dest, TCGv src1, TCGv src2) tcg_gen_movcond_tl(TCG_COND_NE, dest, src2, zero, zero, src1); } -TRANS(ext_w_h, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl) -TRANS(ext_w_b, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl) -TRANS(clo_w, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w) -TRANS(clz_w, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w) -TRANS(cto_w, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w) -TRANS(ctz_w, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w) -TRANS(clo_d, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d) -TRANS(clz_d, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d) -TRANS(cto_d, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d) -TRANS(ctz_d, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d) -TRANS(revb_2h, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h) -TRANS(revb_4h, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h) -TRANS(revb_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w) -TRANS(revb_d, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64) -TRANS(revh_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w) -TRANS(revh_d, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d) -TRANS(bitrev_4b, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap) -TRANS(bitrev_8b, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap) -TRANS(bitrev_w, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w) -TRANS(bitrev_d, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d) -TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz) -TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez) -TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w) -TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d) -TRANS(bstrins_w, gen_bstrins, EXT_SIGN) -TRANS(bstrins_d, gen_bstrins, EXT_NONE) -TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN) -TRANS(bstrpick_d, gen_bstrpick, EXT_NONE) +TRANS(ext_w_h, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext16s_tl) +TRANS(ext_w_b, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_ext8s_tl) +TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w) +TRANS(clz_w, ALL, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w) +TRANS(cto_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w) +TRANS(ctz_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w) +TRANS(clo_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d) +TRANS(clz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d) +TRANS(cto_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d) +TRANS(ctz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d) +TRANS(revb_2h, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h) +TRANS(revb_4h, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h) +TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w) +TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64) +TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w) +TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d) +TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap) +TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap) +TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w) +TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d) +TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz) +TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez) +TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w) +TRANS(bytepick_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d) +TRANS(bstrins_w, ALL, gen_bstrins, EXT_SIGN) +TRANS(bstrins_d, 64, gen_bstrins, EXT_NONE) +TRANS(bstrpick_w, ALL, gen_bstrpick, EXT_SIGN) +TRANS(bstrpick_d, 64, gen_bstrpick, EXT_NONE) diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc index a860f7e733..a4fd2092e5 100644 --- a/target/loongarch/insn_trans/trans_branch.c.inc +++ b/target/loongarch/insn_trans/trans_branch.c.inc @@ -12,7 +12,7 @@ static bool trans_b(DisasContext *ctx, arg_b *a) static bool trans_bl(DisasContext *ctx, arg_bl *a) { - tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4); + tcg_gen_movi_tl(cpu_gpr[1], make_address_pc(ctx, ctx->base.pc_next + 4)); gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs); ctx->base.is_jmp = DISAS_NORETURN; return true; @@ -23,8 +23,9 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); - tcg_gen_addi_tl(cpu_pc, src1, a->imm); - tcg_gen_movi_tl(dest, ctx->base.pc_next + 4); + TCGv addr = make_address_i(ctx, src1, a->imm); + tcg_gen_mov_tl(cpu_pc, addr); + tcg_gen_movi_tl(dest, make_address_pc(ctx, ctx->base.pc_next + 4)); gen_set_gpr(a->rd, dest, EXT_NONE); tcg_gen_lookup_and_goto_ptr(); ctx->base.is_jmp = DISAS_NORETURN; @@ -71,13 +72,13 @@ static bool gen_cz_bc(DisasContext *ctx, arg_c_offs *a, TCGCond cond) return true; } -TRANS(beq, gen_rr_bc, TCG_COND_EQ) -TRANS(bne, gen_rr_bc, TCG_COND_NE) -TRANS(blt, gen_rr_bc, TCG_COND_LT) -TRANS(bge, gen_rr_bc, TCG_COND_GE) -TRANS(bltu, gen_rr_bc, TCG_COND_LTU) -TRANS(bgeu, gen_rr_bc, TCG_COND_GEU) -TRANS(beqz, gen_rz_bc, TCG_COND_EQ) -TRANS(bnez, gen_rz_bc, TCG_COND_NE) -TRANS(bceqz, gen_cz_bc, TCG_COND_EQ) -TRANS(bcnez, gen_cz_bc, TCG_COND_NE) +TRANS(beq, ALL, gen_rr_bc, TCG_COND_EQ) +TRANS(bne, ALL, gen_rr_bc, TCG_COND_NE) +TRANS(blt, ALL, gen_rr_bc, TCG_COND_LT) +TRANS(bge, ALL, gen_rr_bc, TCG_COND_GE) +TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU) +TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU) +TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ) +TRANS(bnez, ALL, gen_rz_bc, TCG_COND_NE) +TRANS(bceqz, 64, gen_cz_bc, TCG_COND_EQ) +TRANS(bcnez, 64, gen_cz_bc, TCG_COND_NE) diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc index 06f4de4515..dd5d02e88c 100644 --- a/target/loongarch/insn_trans/trans_extra.c.inc +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -20,6 +20,10 @@ static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a) TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); + if (!avail_64(ctx)) { + return false; + } + gen_helper_asrtle_d(cpu_env, src1, src2); return true; } @@ -29,6 +33,10 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a) TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); + if (!avail_64(ctx)) { + return false; + } + gen_helper_asrtgt_d(cpu_env, src1, src2); return true; } @@ -89,11 +97,11 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a, return true; } -TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1)) -TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2)) -TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4)) -TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) -TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1)) -TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2)) -TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4)) -TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) +TRANS(crc_w_b_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(1)) +TRANS(crc_w_h_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(2)) +TRANS(crc_w_w_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(4)) +TRANS(crc_w_d_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) +TRANS(crcc_w_b_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(1)) +TRANS(crcc_w_h_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(2)) +TRANS(crcc_w_w_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(4)) +TRANS(crcc_w_d_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc index 21ea47308b..a7ced99fd3 100644 --- a/target/loongarch/insn_trans/trans_farith.c.inc +++ b/target/loongarch/insn_trans/trans_farith.c.inc @@ -67,6 +67,10 @@ static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a) TCGv src1 = get_fpr(ctx, a->fk); TCGv src2 = get_fpr(ctx, a->fj); + if (!avail_FP_SP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_deposit_i64(dest, src1, src2, 0, 31); @@ -81,6 +85,10 @@ static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a) TCGv src1 = get_fpr(ctx, a->fk); TCGv src2 = get_fpr(ctx, a->fj); + if (!avail_FP_DP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_deposit_i64(dest, src1, src2, 0, 63); @@ -94,6 +102,10 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + if (!avail_FP_SP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31)); @@ -108,6 +120,10 @@ static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + if (!avail_FP_DP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63)); @@ -121,6 +137,10 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + if (!avail_FP_SP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_xori_i64(dest, src, 0x80000000); @@ -135,6 +155,10 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a) TCGv dest = get_fpr(ctx, a->fd); TCGv src = get_fpr(ctx, a->fj); + if (!avail_FP_DP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_xori_i64(dest, src, 0x8000000000000000LL); @@ -143,41 +167,41 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a) return true; } -TRANS(fadd_s, gen_fff, gen_helper_fadd_s) -TRANS(fadd_d, gen_fff, gen_helper_fadd_d) -TRANS(fsub_s, gen_fff, gen_helper_fsub_s) -TRANS(fsub_d, gen_fff, gen_helper_fsub_d) -TRANS(fmul_s, gen_fff, gen_helper_fmul_s) -TRANS(fmul_d, gen_fff, gen_helper_fmul_d) -TRANS(fdiv_s, gen_fff, gen_helper_fdiv_s) -TRANS(fdiv_d, gen_fff, gen_helper_fdiv_d) -TRANS(fmax_s, gen_fff, gen_helper_fmax_s) -TRANS(fmax_d, gen_fff, gen_helper_fmax_d) -TRANS(fmin_s, gen_fff, gen_helper_fmin_s) -TRANS(fmin_d, gen_fff, gen_helper_fmin_d) -TRANS(fmaxa_s, gen_fff, gen_helper_fmaxa_s) -TRANS(fmaxa_d, gen_fff, gen_helper_fmaxa_d) -TRANS(fmina_s, gen_fff, gen_helper_fmina_s) -TRANS(fmina_d, gen_fff, gen_helper_fmina_d) -TRANS(fscaleb_s, gen_fff, gen_helper_fscaleb_s) -TRANS(fscaleb_d, gen_fff, gen_helper_fscaleb_d) -TRANS(fsqrt_s, gen_ff, gen_helper_fsqrt_s) -TRANS(fsqrt_d, gen_ff, gen_helper_fsqrt_d) -TRANS(frecip_s, gen_ff, gen_helper_frecip_s) -TRANS(frecip_d, gen_ff, gen_helper_frecip_d) -TRANS(frsqrt_s, gen_ff, gen_helper_frsqrt_s) -TRANS(frsqrt_d, gen_ff, gen_helper_frsqrt_d) -TRANS(flogb_s, gen_ff, gen_helper_flogb_s) -TRANS(flogb_d, gen_ff, gen_helper_flogb_d) -TRANS(fclass_s, gen_ff, gen_helper_fclass_s) -TRANS(fclass_d, gen_ff, gen_helper_fclass_d) -TRANS(fmadd_s, gen_muladd, gen_helper_fmuladd_s, 0) -TRANS(fmadd_d, gen_muladd, gen_helper_fmuladd_d, 0) -TRANS(fmsub_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c) -TRANS(fmsub_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c) -TRANS(fnmadd_s, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result) -TRANS(fnmadd_d, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result) -TRANS(fnmsub_s, gen_muladd, gen_helper_fmuladd_s, +TRANS(fadd_s, FP_SP, gen_fff, gen_helper_fadd_s) +TRANS(fadd_d, FP_DP, gen_fff, gen_helper_fadd_d) +TRANS(fsub_s, FP_SP, gen_fff, gen_helper_fsub_s) +TRANS(fsub_d, FP_DP, gen_fff, gen_helper_fsub_d) +TRANS(fmul_s, FP_SP, gen_fff, gen_helper_fmul_s) +TRANS(fmul_d, FP_DP, gen_fff, gen_helper_fmul_d) +TRANS(fdiv_s, FP_SP, gen_fff, gen_helper_fdiv_s) +TRANS(fdiv_d, FP_DP, gen_fff, gen_helper_fdiv_d) +TRANS(fmax_s, FP_SP, gen_fff, gen_helper_fmax_s) +TRANS(fmax_d, FP_DP, gen_fff, gen_helper_fmax_d) +TRANS(fmin_s, FP_SP, gen_fff, gen_helper_fmin_s) +TRANS(fmin_d, FP_DP, gen_fff, gen_helper_fmin_d) +TRANS(fmaxa_s, FP_SP, gen_fff, gen_helper_fmaxa_s) +TRANS(fmaxa_d, FP_DP, gen_fff, gen_helper_fmaxa_d) +TRANS(fmina_s, FP_SP, gen_fff, gen_helper_fmina_s) +TRANS(fmina_d, FP_DP, gen_fff, gen_helper_fmina_d) +TRANS(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s) +TRANS(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d) +TRANS(fsqrt_s, FP_SP, gen_ff, gen_helper_fsqrt_s) +TRANS(fsqrt_d, FP_DP, gen_ff, gen_helper_fsqrt_d) +TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s) +TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d) +TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s) +TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d) +TRANS(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s) +TRANS(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d) +TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s) +TRANS(fclass_d, FP_DP, gen_ff, gen_helper_fclass_d) +TRANS(fmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, 0) +TRANS(fmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, 0) +TRANS(fmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c) +TRANS(fmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c) +TRANS(fnmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result) +TRANS(fnmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result) +TRANS(fnmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c | float_muladd_negate_result) -TRANS(fnmsub_d, gen_muladd, gen_helper_fmuladd_d, +TRANS(fnmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c | float_muladd_negate_result) diff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc index a78868dbc4..43d5866a67 100644 --- a/target/loongarch/insn_trans/trans_fcmp.c.inc +++ b/target/loongarch/insn_trans/trans_fcmp.c.inc @@ -29,6 +29,10 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a) uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + if (!avail_FP_SP(ctx)) { + return false; + } + CHECK_FPE; var = tcg_temp_new(); @@ -49,6 +53,10 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a) uint32_t flags; void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32); + if (!avail_FP_DP(ctx)) { + return false; + } + CHECK_FPE; var = tcg_temp_new(); diff --git a/target/loongarch/insn_trans/trans_fcnv.c.inc b/target/loongarch/insn_trans/trans_fcnv.c.inc index c1c6918ad1..833c059d6d 100644 --- a/target/loongarch/insn_trans/trans_fcnv.c.inc +++ b/target/loongarch/insn_trans/trans_fcnv.c.inc @@ -3,31 +3,31 @@ * Copyright (c) 2021 Loongson Technology Corporation Limited */ -TRANS(fcvt_s_d, gen_ff, gen_helper_fcvt_s_d) -TRANS(fcvt_d_s, gen_ff, gen_helper_fcvt_d_s) -TRANS(ftintrm_w_s, gen_ff, gen_helper_ftintrm_w_s) -TRANS(ftintrm_w_d, gen_ff, gen_helper_ftintrm_w_d) -TRANS(ftintrm_l_s, gen_ff, gen_helper_ftintrm_l_s) -TRANS(ftintrm_l_d, gen_ff, gen_helper_ftintrm_l_d) -TRANS(ftintrp_w_s, gen_ff, gen_helper_ftintrp_w_s) -TRANS(ftintrp_w_d, gen_ff, gen_helper_ftintrp_w_d) -TRANS(ftintrp_l_s, gen_ff, gen_helper_ftintrp_l_s) -TRANS(ftintrp_l_d, gen_ff, gen_helper_ftintrp_l_d) -TRANS(ftintrz_w_s, gen_ff, gen_helper_ftintrz_w_s) -TRANS(ftintrz_w_d, gen_ff, gen_helper_ftintrz_w_d) -TRANS(ftintrz_l_s, gen_ff, gen_helper_ftintrz_l_s) -TRANS(ftintrz_l_d, gen_ff, gen_helper_ftintrz_l_d) -TRANS(ftintrne_w_s, gen_ff, gen_helper_ftintrne_w_s) -TRANS(ftintrne_w_d, gen_ff, gen_helper_ftintrne_w_d) -TRANS(ftintrne_l_s, gen_ff, gen_helper_ftintrne_l_s) -TRANS(ftintrne_l_d, gen_ff, gen_helper_ftintrne_l_d) -TRANS(ftint_w_s, gen_ff, gen_helper_ftint_w_s) -TRANS(ftint_w_d, gen_ff, gen_helper_ftint_w_d) -TRANS(ftint_l_s, gen_ff, gen_helper_ftint_l_s) -TRANS(ftint_l_d, gen_ff, gen_helper_ftint_l_d) -TRANS(ffint_s_w, gen_ff, gen_helper_ffint_s_w) -TRANS(ffint_s_l, gen_ff, gen_helper_ffint_s_l) -TRANS(ffint_d_w, gen_ff, gen_helper_ffint_d_w) -TRANS(ffint_d_l, gen_ff, gen_helper_ffint_d_l) -TRANS(frint_s, gen_ff, gen_helper_frint_s) -TRANS(frint_d, gen_ff, gen_helper_frint_d) +TRANS(fcvt_s_d, FP_DP, gen_ff, gen_helper_fcvt_s_d) +TRANS(fcvt_d_s, FP_DP, gen_ff, gen_helper_fcvt_d_s) +TRANS(ftintrm_w_s, FP_SP, gen_ff, gen_helper_ftintrm_w_s) +TRANS(ftintrm_w_d, FP_DP, gen_ff, gen_helper_ftintrm_w_d) +TRANS(ftintrm_l_s, FP_SP, gen_ff, gen_helper_ftintrm_l_s) +TRANS(ftintrm_l_d, FP_DP, gen_ff, gen_helper_ftintrm_l_d) +TRANS(ftintrp_w_s, FP_SP, gen_ff, gen_helper_ftintrp_w_s) +TRANS(ftintrp_w_d, FP_DP, gen_ff, gen_helper_ftintrp_w_d) +TRANS(ftintrp_l_s, FP_SP, gen_ff, gen_helper_ftintrp_l_s) +TRANS(ftintrp_l_d, FP_DP, gen_ff, gen_helper_ftintrp_l_d) +TRANS(ftintrz_w_s, FP_SP, gen_ff, gen_helper_ftintrz_w_s) +TRANS(ftintrz_w_d, FP_DP, gen_ff, gen_helper_ftintrz_w_d) +TRANS(ftintrz_l_s, FP_SP, gen_ff, gen_helper_ftintrz_l_s) +TRANS(ftintrz_l_d, FP_DP, gen_ff, gen_helper_ftintrz_l_d) +TRANS(ftintrne_w_s, FP_SP, gen_ff, gen_helper_ftintrne_w_s) +TRANS(ftintrne_w_d, FP_DP, gen_ff, gen_helper_ftintrne_w_d) +TRANS(ftintrne_l_s, FP_SP, gen_ff, gen_helper_ftintrne_l_s) +TRANS(ftintrne_l_d, FP_DP, gen_ff, gen_helper_ftintrne_l_d) +TRANS(ftint_w_s, FP_SP, gen_ff, gen_helper_ftint_w_s) +TRANS(ftint_w_d, FP_DP, gen_ff, gen_helper_ftint_w_d) +TRANS(ftint_l_s, FP_SP, gen_ff, gen_helper_ftint_l_s) +TRANS(ftint_l_d, FP_DP, gen_ff, gen_helper_ftint_l_d) +TRANS(ffint_s_w, FP_SP, gen_ff, gen_helper_ffint_s_w) +TRANS(ffint_s_l, FP_SP, gen_ff, gen_helper_ffint_s_l) +TRANS(ffint_d_w, FP_DP, gen_ff, gen_helper_ffint_d_w) +TRANS(ffint_d_l, FP_DP, gen_ff, gen_helper_ffint_d_l) +TRANS(frint_s, FP_SP, gen_ff, gen_helper_frint_s) +TRANS(frint_d, FP_DP, gen_ff, gen_helper_frint_d) diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc index 91c09fb6d9..5ddb8a473b 100644 --- a/target/loongarch/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/insn_trans/trans_fmemory.c.inc @@ -17,11 +17,7 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) CHECK_FPE; - if (a->imm) { - TCGv temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); @@ -37,11 +33,7 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop) CHECK_FPE; - if (a->imm) { - TCGv temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop); @@ -57,8 +49,7 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop) CHECK_FPE; - addr = tcg_temp_new(); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); set_fpr(a->fd, dest); @@ -75,8 +66,7 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop) CHECK_FPE; - addr = tcg_temp_new(); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); return true; @@ -91,9 +81,8 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop) CHECK_FPE; - addr = tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); set_fpr(a->fd, dest); @@ -110,9 +99,8 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop) CHECK_FPE; - addr = tcg_temp_new(); gen_helper_asrtgt_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); return true; @@ -127,9 +115,8 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop) CHECK_FPE; - addr = tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); maybe_nanbox_load(dest, mop); set_fpr(a->fd, dest); @@ -146,27 +133,26 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop) CHECK_FPE; - addr = tcg_temp_new(); gen_helper_asrtle_d(cpu_env, src1, src2); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop); return true; } -TRANS(fld_s, gen_fload_i, MO_TEUL) -TRANS(fst_s, gen_fstore_i, MO_TEUL) -TRANS(fld_d, gen_fload_i, MO_TEUQ) -TRANS(fst_d, gen_fstore_i, MO_TEUQ) -TRANS(fldx_s, gen_floadx, MO_TEUL) -TRANS(fldx_d, gen_floadx, MO_TEUQ) -TRANS(fstx_s, gen_fstorex, MO_TEUL) -TRANS(fstx_d, gen_fstorex, MO_TEUQ) -TRANS(fldgt_s, gen_fload_gt, MO_TEUL) -TRANS(fldgt_d, gen_fload_gt, MO_TEUQ) -TRANS(fldle_s, gen_fload_le, MO_TEUL) -TRANS(fldle_d, gen_fload_le, MO_TEUQ) -TRANS(fstgt_s, gen_fstore_gt, MO_TEUL) -TRANS(fstgt_d, gen_fstore_gt, MO_TEUQ) -TRANS(fstle_s, gen_fstore_le, MO_TEUL) -TRANS(fstle_d, gen_fstore_le, MO_TEUQ) +TRANS(fld_s, FP_SP, gen_fload_i, MO_TEUL) +TRANS(fst_s, FP_SP, gen_fstore_i, MO_TEUL) +TRANS(fld_d, FP_DP, gen_fload_i, MO_TEUQ) +TRANS(fst_d, FP_DP, gen_fstore_i, MO_TEUQ) +TRANS(fldx_s, FP_SP, gen_floadx, MO_TEUL) +TRANS(fldx_d, FP_DP, gen_floadx, MO_TEUQ) +TRANS(fstx_s, FP_SP, gen_fstorex, MO_TEUL) +TRANS(fstx_d, FP_DP, gen_fstorex, MO_TEUQ) +TRANS(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL) +TRANS(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ) +TRANS(fldle_s, FP_SP, gen_fload_le, MO_TEUL) +TRANS(fldle_d, FP_DP, gen_fload_le, MO_TEUQ) +TRANS(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL) +TRANS(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ) +TRANS(fstle_s, FP_SP, gen_fstore_le, MO_TEUL) +TRANS(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ) diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc index 5af0dd1b66..928e127820 100644 --- a/target/loongarch/insn_trans/trans_fmov.c.inc +++ b/target/loongarch/insn_trans/trans_fmov.c.inc @@ -15,6 +15,10 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a) TCGv src2 = get_fpr(ctx, a->fk); TCGv cond; + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; cond = tcg_temp_new(); @@ -48,6 +52,10 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a, TCGv src = gpr_src(ctx, a->rj, EXT_NONE); TCGv dest = get_fpr(ctx, a->fd); + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; func(dest, src); @@ -62,6 +70,10 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a, TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src = get_fpr(ctx, a->fj); + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; func(dest, src); @@ -75,6 +87,10 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a) uint32_t mask = fcsr_mask[a->fcsrd]; TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE); + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; if (mask == UINT32_MAX) { @@ -105,6 +121,10 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a) { TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0)); @@ -134,6 +154,10 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a) TCGv t0; TCGv src = get_fpr(ctx, a->fj); + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; t0 = tcg_temp_new(); @@ -147,6 +171,10 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a) { TCGv dest = get_fpr(ctx, a->fd); + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_ld8u_tl(dest, cpu_env, @@ -160,6 +188,10 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) { TCGv t0; + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; t0 = tcg_temp_new(); @@ -171,6 +203,10 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a) static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) { + if (!avail_FP(ctx)) { + return false; + } + CHECK_FPE; tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env, @@ -178,11 +214,11 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a) return true; } -TRANS(fmov_s, gen_f2f, tcg_gen_mov_tl, true) -TRANS(fmov_d, gen_f2f, tcg_gen_mov_tl, false) -TRANS(movgr2fr_w, gen_r2f, gen_movgr2fr_w) -TRANS(movgr2fr_d, gen_r2f, tcg_gen_mov_tl) -TRANS(movgr2frh_w, gen_r2f, gen_movgr2frh_w) -TRANS(movfr2gr_s, gen_f2r, tcg_gen_ext32s_tl) -TRANS(movfr2gr_d, gen_f2r, tcg_gen_mov_tl) -TRANS(movfrh2gr_s, gen_f2r, gen_movfrh2gr_s) +TRANS(fmov_s, FP_SP, gen_f2f, tcg_gen_mov_tl, true) +TRANS(fmov_d, FP_DP, gen_f2f, tcg_gen_mov_tl, false) +TRANS(movgr2fr_w, FP_SP, gen_r2f, gen_movgr2fr_w) +TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl) +TRANS(movgr2frh_w, FP_DP, gen_r2f, gen_movgr2frh_w) +TRANS(movfr2gr_s, FP_SP, gen_f2r, tcg_gen_ext32s_tl) +TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl) +TRANS(movfrh2gr_s, FP_DP, gen_f2r, gen_movfrh2gr_s) diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 68779daff6..5fbf2718f7 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -135,16 +135,20 @@ static bool gvec_subi(DisasContext *ctx, arg_vv_i *a, MemOp mop) return true; } -TRANS(vadd_b, gvec_vvv, MO_8, tcg_gen_gvec_add) -TRANS(vadd_h, gvec_vvv, MO_16, tcg_gen_gvec_add) -TRANS(vadd_w, gvec_vvv, MO_32, tcg_gen_gvec_add) -TRANS(vadd_d, gvec_vvv, MO_64, tcg_gen_gvec_add) +TRANS(vadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_add) +TRANS(vadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_add) +TRANS(vadd_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_add) +TRANS(vadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_add) #define VADDSUB_Q(NAME) \ static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \ { \ TCGv_i64 rh, rl, ah, al, bh, bl; \ \ + if (!avail_LSX(ctx)) { \ + return false; \ + } \ + \ CHECK_SXE; \ \ rh = tcg_temp_new_i64(); \ @@ -170,58 +174,58 @@ static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \ VADDSUB_Q(add) VADDSUB_Q(sub) -TRANS(vsub_b, gvec_vvv, MO_8, tcg_gen_gvec_sub) -TRANS(vsub_h, gvec_vvv, MO_16, tcg_gen_gvec_sub) -TRANS(vsub_w, gvec_vvv, MO_32, tcg_gen_gvec_sub) -TRANS(vsub_d, gvec_vvv, MO_64, tcg_gen_gvec_sub) - -TRANS(vaddi_bu, gvec_vv_i, MO_8, tcg_gen_gvec_addi) -TRANS(vaddi_hu, gvec_vv_i, MO_16, tcg_gen_gvec_addi) -TRANS(vaddi_wu, gvec_vv_i, MO_32, tcg_gen_gvec_addi) -TRANS(vaddi_du, gvec_vv_i, MO_64, tcg_gen_gvec_addi) -TRANS(vsubi_bu, gvec_subi, MO_8) -TRANS(vsubi_hu, gvec_subi, MO_16) -TRANS(vsubi_wu, gvec_subi, MO_32) -TRANS(vsubi_du, gvec_subi, MO_64) - -TRANS(vneg_b, gvec_vv, MO_8, tcg_gen_gvec_neg) -TRANS(vneg_h, gvec_vv, MO_16, tcg_gen_gvec_neg) -TRANS(vneg_w, gvec_vv, MO_32, tcg_gen_gvec_neg) -TRANS(vneg_d, gvec_vv, MO_64, tcg_gen_gvec_neg) - -TRANS(vsadd_b, gvec_vvv, MO_8, tcg_gen_gvec_ssadd) -TRANS(vsadd_h, gvec_vvv, MO_16, tcg_gen_gvec_ssadd) -TRANS(vsadd_w, gvec_vvv, MO_32, tcg_gen_gvec_ssadd) -TRANS(vsadd_d, gvec_vvv, MO_64, tcg_gen_gvec_ssadd) -TRANS(vsadd_bu, gvec_vvv, MO_8, tcg_gen_gvec_usadd) -TRANS(vsadd_hu, gvec_vvv, MO_16, tcg_gen_gvec_usadd) -TRANS(vsadd_wu, gvec_vvv, MO_32, tcg_gen_gvec_usadd) -TRANS(vsadd_du, gvec_vvv, MO_64, tcg_gen_gvec_usadd) -TRANS(vssub_b, gvec_vvv, MO_8, tcg_gen_gvec_sssub) -TRANS(vssub_h, gvec_vvv, MO_16, tcg_gen_gvec_sssub) -TRANS(vssub_w, gvec_vvv, MO_32, tcg_gen_gvec_sssub) -TRANS(vssub_d, gvec_vvv, MO_64, tcg_gen_gvec_sssub) -TRANS(vssub_bu, gvec_vvv, MO_8, tcg_gen_gvec_ussub) -TRANS(vssub_hu, gvec_vvv, MO_16, tcg_gen_gvec_ussub) -TRANS(vssub_wu, gvec_vvv, MO_32, tcg_gen_gvec_ussub) -TRANS(vssub_du, gvec_vvv, MO_64, tcg_gen_gvec_ussub) - -TRANS(vhaddw_h_b, gen_vvv, gen_helper_vhaddw_h_b) -TRANS(vhaddw_w_h, gen_vvv, gen_helper_vhaddw_w_h) -TRANS(vhaddw_d_w, gen_vvv, gen_helper_vhaddw_d_w) -TRANS(vhaddw_q_d, gen_vvv, gen_helper_vhaddw_q_d) -TRANS(vhaddw_hu_bu, gen_vvv, gen_helper_vhaddw_hu_bu) -TRANS(vhaddw_wu_hu, gen_vvv, gen_helper_vhaddw_wu_hu) -TRANS(vhaddw_du_wu, gen_vvv, gen_helper_vhaddw_du_wu) -TRANS(vhaddw_qu_du, gen_vvv, gen_helper_vhaddw_qu_du) -TRANS(vhsubw_h_b, gen_vvv, gen_helper_vhsubw_h_b) -TRANS(vhsubw_w_h, gen_vvv, gen_helper_vhsubw_w_h) -TRANS(vhsubw_d_w, gen_vvv, gen_helper_vhsubw_d_w) -TRANS(vhsubw_q_d, gen_vvv, gen_helper_vhsubw_q_d) -TRANS(vhsubw_hu_bu, gen_vvv, gen_helper_vhsubw_hu_bu) -TRANS(vhsubw_wu_hu, gen_vvv, gen_helper_vhsubw_wu_hu) -TRANS(vhsubw_du_wu, gen_vvv, gen_helper_vhsubw_du_wu) -TRANS(vhsubw_qu_du, gen_vvv, gen_helper_vhsubw_qu_du) +TRANS(vsub_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sub) +TRANS(vsub_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sub) +TRANS(vsub_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sub) +TRANS(vsub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sub) + +TRANS(vaddi_bu, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_addi) +TRANS(vaddi_hu, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_addi) +TRANS(vaddi_wu, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_addi) +TRANS(vaddi_du, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_addi) +TRANS(vsubi_bu, LSX, gvec_subi, MO_8) +TRANS(vsubi_hu, LSX, gvec_subi, MO_16) +TRANS(vsubi_wu, LSX, gvec_subi, MO_32) +TRANS(vsubi_du, LSX, gvec_subi, MO_64) + +TRANS(vneg_b, LSX, gvec_vv, MO_8, tcg_gen_gvec_neg) +TRANS(vneg_h, LSX, gvec_vv, MO_16, tcg_gen_gvec_neg) +TRANS(vneg_w, LSX, gvec_vv, MO_32, tcg_gen_gvec_neg) +TRANS(vneg_d, LSX, gvec_vv, MO_64, tcg_gen_gvec_neg) + +TRANS(vsadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ssadd) +TRANS(vsadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ssadd) +TRANS(vsadd_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ssadd) +TRANS(vsadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ssadd) +TRANS(vsadd_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_usadd) +TRANS(vsadd_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_usadd) +TRANS(vsadd_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_usadd) +TRANS(vsadd_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_usadd) +TRANS(vssub_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sssub) +TRANS(vssub_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sssub) +TRANS(vssub_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sssub) +TRANS(vssub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sssub) +TRANS(vssub_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ussub) +TRANS(vssub_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ussub) +TRANS(vssub_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ussub) +TRANS(vssub_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ussub) + +TRANS(vhaddw_h_b, LSX, gen_vvv, gen_helper_vhaddw_h_b) +TRANS(vhaddw_w_h, LSX, gen_vvv, gen_helper_vhaddw_w_h) +TRANS(vhaddw_d_w, LSX, gen_vvv, gen_helper_vhaddw_d_w) +TRANS(vhaddw_q_d, LSX, gen_vvv, gen_helper_vhaddw_q_d) +TRANS(vhaddw_hu_bu, LSX, gen_vvv, gen_helper_vhaddw_hu_bu) +TRANS(vhaddw_wu_hu, LSX, gen_vvv, gen_helper_vhaddw_wu_hu) +TRANS(vhaddw_du_wu, LSX, gen_vvv, gen_helper_vhaddw_du_wu) +TRANS(vhaddw_qu_du, LSX, gen_vvv, gen_helper_vhaddw_qu_du) +TRANS(vhsubw_h_b, LSX, gen_vvv, gen_helper_vhsubw_h_b) +TRANS(vhsubw_w_h, LSX, gen_vvv, gen_helper_vhsubw_w_h) +TRANS(vhsubw_d_w, LSX, gen_vvv, gen_helper_vhsubw_d_w) +TRANS(vhsubw_q_d, LSX, gen_vvv, gen_helper_vhsubw_q_d) +TRANS(vhsubw_hu_bu, LSX, gen_vvv, gen_helper_vhsubw_hu_bu) +TRANS(vhsubw_wu_hu, LSX, gen_vvv, gen_helper_vhsubw_wu_hu) +TRANS(vhsubw_du_wu, LSX, gen_vvv, gen_helper_vhsubw_du_wu) +TRANS(vhsubw_qu_du, LSX, gen_vvv, gen_helper_vhsubw_qu_du) static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -301,10 +305,10 @@ static void do_vaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vaddwev_h_b, gvec_vvv, MO_8, do_vaddwev_s) -TRANS(vaddwev_w_h, gvec_vvv, MO_16, do_vaddwev_s) -TRANS(vaddwev_d_w, gvec_vvv, MO_32, do_vaddwev_s) -TRANS(vaddwev_q_d, gvec_vvv, MO_64, do_vaddwev_s) +TRANS(vaddwev_h_b, LSX, gvec_vvv, MO_8, do_vaddwev_s) +TRANS(vaddwev_w_h, LSX, gvec_vvv, MO_16, do_vaddwev_s) +TRANS(vaddwev_d_w, LSX, gvec_vvv, MO_32, do_vaddwev_s) +TRANS(vaddwev_q_d, LSX, gvec_vvv, MO_64, do_vaddwev_s) static void gen_vaddwod_w_h(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) { @@ -380,10 +384,10 @@ static void do_vaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vaddwod_h_b, gvec_vvv, MO_8, do_vaddwod_s) -TRANS(vaddwod_w_h, gvec_vvv, MO_16, do_vaddwod_s) -TRANS(vaddwod_d_w, gvec_vvv, MO_32, do_vaddwod_s) -TRANS(vaddwod_q_d, gvec_vvv, MO_64, do_vaddwod_s) +TRANS(vaddwod_h_b, LSX, gvec_vvv, MO_8, do_vaddwod_s) +TRANS(vaddwod_w_h, LSX, gvec_vvv, MO_16, do_vaddwod_s) +TRANS(vaddwod_d_w, LSX, gvec_vvv, MO_32, do_vaddwod_s) +TRANS(vaddwod_q_d, LSX, gvec_vvv, MO_64, do_vaddwod_s) static void gen_vsubwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -463,10 +467,10 @@ static void do_vsubwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vsubwev_h_b, gvec_vvv, MO_8, do_vsubwev_s) -TRANS(vsubwev_w_h, gvec_vvv, MO_16, do_vsubwev_s) -TRANS(vsubwev_d_w, gvec_vvv, MO_32, do_vsubwev_s) -TRANS(vsubwev_q_d, gvec_vvv, MO_64, do_vsubwev_s) +TRANS(vsubwev_h_b, LSX, gvec_vvv, MO_8, do_vsubwev_s) +TRANS(vsubwev_w_h, LSX, gvec_vvv, MO_16, do_vsubwev_s) +TRANS(vsubwev_d_w, LSX, gvec_vvv, MO_32, do_vsubwev_s) +TRANS(vsubwev_q_d, LSX, gvec_vvv, MO_64, do_vsubwev_s) static void gen_vsubwod_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -542,10 +546,10 @@ static void do_vsubwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vsubwod_h_b, gvec_vvv, MO_8, do_vsubwod_s) -TRANS(vsubwod_w_h, gvec_vvv, MO_16, do_vsubwod_s) -TRANS(vsubwod_d_w, gvec_vvv, MO_32, do_vsubwod_s) -TRANS(vsubwod_q_d, gvec_vvv, MO_64, do_vsubwod_s) +TRANS(vsubwod_h_b, LSX, gvec_vvv, MO_8, do_vsubwod_s) +TRANS(vsubwod_w_h, LSX, gvec_vvv, MO_16, do_vsubwod_s) +TRANS(vsubwod_d_w, LSX, gvec_vvv, MO_32, do_vsubwod_s) +TRANS(vsubwod_q_d, LSX, gvec_vvv, MO_64, do_vsubwod_s) static void gen_vaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -617,10 +621,10 @@ static void do_vaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vaddwev_h_bu, gvec_vvv, MO_8, do_vaddwev_u) -TRANS(vaddwev_w_hu, gvec_vvv, MO_16, do_vaddwev_u) -TRANS(vaddwev_d_wu, gvec_vvv, MO_32, do_vaddwev_u) -TRANS(vaddwev_q_du, gvec_vvv, MO_64, do_vaddwev_u) +TRANS(vaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vaddwev_u) +TRANS(vaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vaddwev_u) +TRANS(vaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vaddwev_u) +TRANS(vaddwev_q_du, LSX, gvec_vvv, MO_64, do_vaddwev_u) static void gen_vaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -696,10 +700,10 @@ static void do_vaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vaddwod_h_bu, gvec_vvv, MO_8, do_vaddwod_u) -TRANS(vaddwod_w_hu, gvec_vvv, MO_16, do_vaddwod_u) -TRANS(vaddwod_d_wu, gvec_vvv, MO_32, do_vaddwod_u) -TRANS(vaddwod_q_du, gvec_vvv, MO_64, do_vaddwod_u) +TRANS(vaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vaddwod_u) +TRANS(vaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vaddwod_u) +TRANS(vaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vaddwod_u) +TRANS(vaddwod_q_du, LSX, gvec_vvv, MO_64, do_vaddwod_u) static void gen_vsubwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -771,10 +775,10 @@ static void do_vsubwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vsubwev_h_bu, gvec_vvv, MO_8, do_vsubwev_u) -TRANS(vsubwev_w_hu, gvec_vvv, MO_16, do_vsubwev_u) -TRANS(vsubwev_d_wu, gvec_vvv, MO_32, do_vsubwev_u) -TRANS(vsubwev_q_du, gvec_vvv, MO_64, do_vsubwev_u) +TRANS(vsubwev_h_bu, LSX, gvec_vvv, MO_8, do_vsubwev_u) +TRANS(vsubwev_w_hu, LSX, gvec_vvv, MO_16, do_vsubwev_u) +TRANS(vsubwev_d_wu, LSX, gvec_vvv, MO_32, do_vsubwev_u) +TRANS(vsubwev_q_du, LSX, gvec_vvv, MO_64, do_vsubwev_u) static void gen_vsubwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -850,10 +854,10 @@ static void do_vsubwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vsubwod_h_bu, gvec_vvv, MO_8, do_vsubwod_u) -TRANS(vsubwod_w_hu, gvec_vvv, MO_16, do_vsubwod_u) -TRANS(vsubwod_d_wu, gvec_vvv, MO_32, do_vsubwod_u) -TRANS(vsubwod_q_du, gvec_vvv, MO_64, do_vsubwod_u) +TRANS(vsubwod_h_bu, LSX, gvec_vvv, MO_8, do_vsubwod_u) +TRANS(vsubwod_w_hu, LSX, gvec_vvv, MO_16, do_vsubwod_u) +TRANS(vsubwod_d_wu, LSX, gvec_vvv, MO_32, do_vsubwod_u) +TRANS(vsubwod_q_du, LSX, gvec_vvv, MO_64, do_vsubwod_u) static void gen_vaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -933,10 +937,10 @@ static void do_vaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vaddwev_h_bu_b, gvec_vvv, MO_8, do_vaddwev_u_s) -TRANS(vaddwev_w_hu_h, gvec_vvv, MO_16, do_vaddwev_u_s) -TRANS(vaddwev_d_wu_w, gvec_vvv, MO_32, do_vaddwev_u_s) -TRANS(vaddwev_q_du_d, gvec_vvv, MO_64, do_vaddwev_u_s) +TRANS(vaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vaddwev_u_s) +TRANS(vaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vaddwev_u_s) +TRANS(vaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vaddwev_u_s) +TRANS(vaddwev_q_du_d, LSX, gvec_vvv, MO_64, do_vaddwev_u_s) static void gen_vaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -1013,10 +1017,10 @@ static void do_vaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vaddwod_h_bu_b, gvec_vvv, MO_8, do_vaddwod_u_s) -TRANS(vaddwod_w_hu_h, gvec_vvv, MO_16, do_vaddwod_u_s) -TRANS(vaddwod_d_wu_w, gvec_vvv, MO_32, do_vaddwod_u_s) -TRANS(vaddwod_q_du_d, gvec_vvv, MO_64, do_vaddwod_u_s) +TRANS(vaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vaddwod_u_s) +TRANS(vaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vaddwod_u_s) +TRANS(vaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vaddwod_u_s) +TRANS(vaddwod_q_du_d, LSX, gvec_vvv, MO_64, do_vaddwod_u_s) static void do_vavg(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b, void (*gen_shr_vec)(unsigned, TCGv_vec, @@ -1125,14 +1129,14 @@ static void do_vavg_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vavg_b, gvec_vvv, MO_8, do_vavg_s) -TRANS(vavg_h, gvec_vvv, MO_16, do_vavg_s) -TRANS(vavg_w, gvec_vvv, MO_32, do_vavg_s) -TRANS(vavg_d, gvec_vvv, MO_64, do_vavg_s) -TRANS(vavg_bu, gvec_vvv, MO_8, do_vavg_u) -TRANS(vavg_hu, gvec_vvv, MO_16, do_vavg_u) -TRANS(vavg_wu, gvec_vvv, MO_32, do_vavg_u) -TRANS(vavg_du, gvec_vvv, MO_64, do_vavg_u) +TRANS(vavg_b, LSX, gvec_vvv, MO_8, do_vavg_s) +TRANS(vavg_h, LSX, gvec_vvv, MO_16, do_vavg_s) +TRANS(vavg_w, LSX, gvec_vvv, MO_32, do_vavg_s) +TRANS(vavg_d, LSX, gvec_vvv, MO_64, do_vavg_s) +TRANS(vavg_bu, LSX, gvec_vvv, MO_8, do_vavg_u) +TRANS(vavg_hu, LSX, gvec_vvv, MO_16, do_vavg_u) +TRANS(vavg_wu, LSX, gvec_vvv, MO_32, do_vavg_u) +TRANS(vavg_du, LSX, gvec_vvv, MO_64, do_vavg_u) static void do_vavgr_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz) @@ -1206,14 +1210,14 @@ static void do_vavgr_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vavgr_b, gvec_vvv, MO_8, do_vavgr_s) -TRANS(vavgr_h, gvec_vvv, MO_16, do_vavgr_s) -TRANS(vavgr_w, gvec_vvv, MO_32, do_vavgr_s) -TRANS(vavgr_d, gvec_vvv, MO_64, do_vavgr_s) -TRANS(vavgr_bu, gvec_vvv, MO_8, do_vavgr_u) -TRANS(vavgr_hu, gvec_vvv, MO_16, do_vavgr_u) -TRANS(vavgr_wu, gvec_vvv, MO_32, do_vavgr_u) -TRANS(vavgr_du, gvec_vvv, MO_64, do_vavgr_u) +TRANS(vavgr_b, LSX, gvec_vvv, MO_8, do_vavgr_s) +TRANS(vavgr_h, LSX, gvec_vvv, MO_16, do_vavgr_s) +TRANS(vavgr_w, LSX, gvec_vvv, MO_32, do_vavgr_s) +TRANS(vavgr_d, LSX, gvec_vvv, MO_64, do_vavgr_s) +TRANS(vavgr_bu, LSX, gvec_vvv, MO_8, do_vavgr_u) +TRANS(vavgr_hu, LSX, gvec_vvv, MO_16, do_vavgr_u) +TRANS(vavgr_wu, LSX, gvec_vvv, MO_32, do_vavgr_u) +TRANS(vavgr_du, LSX, gvec_vvv, MO_64, do_vavgr_u) static void gen_vabsd_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -1301,14 +1305,14 @@ static void do_vabsd_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vabsd_b, gvec_vvv, MO_8, do_vabsd_s) -TRANS(vabsd_h, gvec_vvv, MO_16, do_vabsd_s) -TRANS(vabsd_w, gvec_vvv, MO_32, do_vabsd_s) -TRANS(vabsd_d, gvec_vvv, MO_64, do_vabsd_s) -TRANS(vabsd_bu, gvec_vvv, MO_8, do_vabsd_u) -TRANS(vabsd_hu, gvec_vvv, MO_16, do_vabsd_u) -TRANS(vabsd_wu, gvec_vvv, MO_32, do_vabsd_u) -TRANS(vabsd_du, gvec_vvv, MO_64, do_vabsd_u) +TRANS(vabsd_b, LSX, gvec_vvv, MO_8, do_vabsd_s) +TRANS(vabsd_h, LSX, gvec_vvv, MO_16, do_vabsd_s) +TRANS(vabsd_w, LSX, gvec_vvv, MO_32, do_vabsd_s) +TRANS(vabsd_d, LSX, gvec_vvv, MO_64, do_vabsd_s) +TRANS(vabsd_bu, LSX, gvec_vvv, MO_8, do_vabsd_u) +TRANS(vabsd_hu, LSX, gvec_vvv, MO_16, do_vabsd_u) +TRANS(vabsd_wu, LSX, gvec_vvv, MO_32, do_vabsd_u) +TRANS(vabsd_du, LSX, gvec_vvv, MO_64, do_vabsd_u) static void gen_vadda(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -1358,28 +1362,28 @@ static void do_vadda(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vadda_b, gvec_vvv, MO_8, do_vadda) -TRANS(vadda_h, gvec_vvv, MO_16, do_vadda) -TRANS(vadda_w, gvec_vvv, MO_32, do_vadda) -TRANS(vadda_d, gvec_vvv, MO_64, do_vadda) - -TRANS(vmax_b, gvec_vvv, MO_8, tcg_gen_gvec_smax) -TRANS(vmax_h, gvec_vvv, MO_16, tcg_gen_gvec_smax) -TRANS(vmax_w, gvec_vvv, MO_32, tcg_gen_gvec_smax) -TRANS(vmax_d, gvec_vvv, MO_64, tcg_gen_gvec_smax) -TRANS(vmax_bu, gvec_vvv, MO_8, tcg_gen_gvec_umax) -TRANS(vmax_hu, gvec_vvv, MO_16, tcg_gen_gvec_umax) -TRANS(vmax_wu, gvec_vvv, MO_32, tcg_gen_gvec_umax) -TRANS(vmax_du, gvec_vvv, MO_64, tcg_gen_gvec_umax) - -TRANS(vmin_b, gvec_vvv, MO_8, tcg_gen_gvec_smin) -TRANS(vmin_h, gvec_vvv, MO_16, tcg_gen_gvec_smin) -TRANS(vmin_w, gvec_vvv, MO_32, tcg_gen_gvec_smin) -TRANS(vmin_d, gvec_vvv, MO_64, tcg_gen_gvec_smin) -TRANS(vmin_bu, gvec_vvv, MO_8, tcg_gen_gvec_umin) -TRANS(vmin_hu, gvec_vvv, MO_16, tcg_gen_gvec_umin) -TRANS(vmin_wu, gvec_vvv, MO_32, tcg_gen_gvec_umin) -TRANS(vmin_du, gvec_vvv, MO_64, tcg_gen_gvec_umin) +TRANS(vadda_b, LSX, gvec_vvv, MO_8, do_vadda) +TRANS(vadda_h, LSX, gvec_vvv, MO_16, do_vadda) +TRANS(vadda_w, LSX, gvec_vvv, MO_32, do_vadda) +TRANS(vadda_d, LSX, gvec_vvv, MO_64, do_vadda) + +TRANS(vmax_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smax) +TRANS(vmax_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smax) +TRANS(vmax_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_smax) +TRANS(vmax_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_smax) +TRANS(vmax_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umax) +TRANS(vmax_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umax) +TRANS(vmax_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umax) +TRANS(vmax_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umax) + +TRANS(vmin_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smin) +TRANS(vmin_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smin) +TRANS(vmin_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_smin) +TRANS(vmin_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_smin) +TRANS(vmin_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umin) +TRANS(vmin_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umin) +TRANS(vmin_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umin) +TRANS(vmin_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umin) static void gen_vmini_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) { @@ -1473,14 +1477,14 @@ static void do_vmini_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); } -TRANS(vmini_b, gvec_vv_i, MO_8, do_vmini_s) -TRANS(vmini_h, gvec_vv_i, MO_16, do_vmini_s) -TRANS(vmini_w, gvec_vv_i, MO_32, do_vmini_s) -TRANS(vmini_d, gvec_vv_i, MO_64, do_vmini_s) -TRANS(vmini_bu, gvec_vv_i, MO_8, do_vmini_u) -TRANS(vmini_hu, gvec_vv_i, MO_16, do_vmini_u) -TRANS(vmini_wu, gvec_vv_i, MO_32, do_vmini_u) -TRANS(vmini_du, gvec_vv_i, MO_64, do_vmini_u) +TRANS(vmini_b, LSX, gvec_vv_i, MO_8, do_vmini_s) +TRANS(vmini_h, LSX, gvec_vv_i, MO_16, do_vmini_s) +TRANS(vmini_w, LSX, gvec_vv_i, MO_32, do_vmini_s) +TRANS(vmini_d, LSX, gvec_vv_i, MO_64, do_vmini_s) +TRANS(vmini_bu, LSX, gvec_vv_i, MO_8, do_vmini_u) +TRANS(vmini_hu, LSX, gvec_vv_i, MO_16, do_vmini_u) +TRANS(vmini_wu, LSX, gvec_vv_i, MO_32, do_vmini_u) +TRANS(vmini_du, LSX, gvec_vv_i, MO_64, do_vmini_u) static void do_vmaxi_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, int64_t imm, uint32_t oprsz, uint32_t maxsz) @@ -1554,19 +1558,19 @@ static void do_vmaxi_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); } -TRANS(vmaxi_b, gvec_vv_i, MO_8, do_vmaxi_s) -TRANS(vmaxi_h, gvec_vv_i, MO_16, do_vmaxi_s) -TRANS(vmaxi_w, gvec_vv_i, MO_32, do_vmaxi_s) -TRANS(vmaxi_d, gvec_vv_i, MO_64, do_vmaxi_s) -TRANS(vmaxi_bu, gvec_vv_i, MO_8, do_vmaxi_u) -TRANS(vmaxi_hu, gvec_vv_i, MO_16, do_vmaxi_u) -TRANS(vmaxi_wu, gvec_vv_i, MO_32, do_vmaxi_u) -TRANS(vmaxi_du, gvec_vv_i, MO_64, do_vmaxi_u) +TRANS(vmaxi_b, LSX, gvec_vv_i, MO_8, do_vmaxi_s) +TRANS(vmaxi_h, LSX, gvec_vv_i, MO_16, do_vmaxi_s) +TRANS(vmaxi_w, LSX, gvec_vv_i, MO_32, do_vmaxi_s) +TRANS(vmaxi_d, LSX, gvec_vv_i, MO_64, do_vmaxi_s) +TRANS(vmaxi_bu, LSX, gvec_vv_i, MO_8, do_vmaxi_u) +TRANS(vmaxi_hu, LSX, gvec_vv_i, MO_16, do_vmaxi_u) +TRANS(vmaxi_wu, LSX, gvec_vv_i, MO_32, do_vmaxi_u) +TRANS(vmaxi_du, LSX, gvec_vv_i, MO_64, do_vmaxi_u) -TRANS(vmul_b, gvec_vvv, MO_8, tcg_gen_gvec_mul) -TRANS(vmul_h, gvec_vvv, MO_16, tcg_gen_gvec_mul) -TRANS(vmul_w, gvec_vvv, MO_32, tcg_gen_gvec_mul) -TRANS(vmul_d, gvec_vvv, MO_64, tcg_gen_gvec_mul) +TRANS(vmul_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_mul) +TRANS(vmul_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_mul) +TRANS(vmul_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_mul) +TRANS(vmul_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_mul) static void gen_vmuh_w(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) { @@ -1607,10 +1611,10 @@ static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmuh_b, gvec_vvv, MO_8, do_vmuh_s) -TRANS(vmuh_h, gvec_vvv, MO_16, do_vmuh_s) -TRANS(vmuh_w, gvec_vvv, MO_32, do_vmuh_s) -TRANS(vmuh_d, gvec_vvv, MO_64, do_vmuh_s) +TRANS(vmuh_b, LSX, gvec_vvv, MO_8, do_vmuh_s) +TRANS(vmuh_h, LSX, gvec_vvv, MO_16, do_vmuh_s) +TRANS(vmuh_w, LSX, gvec_vvv, MO_32, do_vmuh_s) +TRANS(vmuh_d, LSX, gvec_vvv, MO_64, do_vmuh_s) static void gen_vmuh_wu(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b) { @@ -1651,10 +1655,10 @@ static void do_vmuh_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmuh_bu, gvec_vvv, MO_8, do_vmuh_u) -TRANS(vmuh_hu, gvec_vvv, MO_16, do_vmuh_u) -TRANS(vmuh_wu, gvec_vvv, MO_32, do_vmuh_u) -TRANS(vmuh_du, gvec_vvv, MO_64, do_vmuh_u) +TRANS(vmuh_bu, LSX, gvec_vvv, MO_8, do_vmuh_u) +TRANS(vmuh_hu, LSX, gvec_vvv, MO_16, do_vmuh_u) +TRANS(vmuh_wu, LSX, gvec_vvv, MO_32, do_vmuh_u) +TRANS(vmuh_du, LSX, gvec_vvv, MO_64, do_vmuh_u) static void gen_vmulwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -1724,9 +1728,9 @@ static void do_vmulwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmulwev_h_b, gvec_vvv, MO_8, do_vmulwev_s) -TRANS(vmulwev_w_h, gvec_vvv, MO_16, do_vmulwev_s) -TRANS(vmulwev_d_w, gvec_vvv, MO_32, do_vmulwev_s) +TRANS(vmulwev_h_b, LSX, gvec_vvv, MO_8, do_vmulwev_s) +TRANS(vmulwev_w_h, LSX, gvec_vvv, MO_16, do_vmulwev_s) +TRANS(vmulwev_d_w, LSX, gvec_vvv, MO_32, do_vmulwev_s) static void tcg_gen_mulus2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2) @@ -1739,6 +1743,10 @@ static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \ { \ TCGv_i64 rh, rl, arg1, arg2; \ \ + if (!avail_LSX(ctx)) { \ + return false; \ + } \ + \ rh = tcg_temp_new_i64(); \ rl = tcg_temp_new_i64(); \ arg1 = tcg_temp_new_i64(); \ @@ -1828,9 +1836,9 @@ static void do_vmulwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmulwod_h_b, gvec_vvv, MO_8, do_vmulwod_s) -TRANS(vmulwod_w_h, gvec_vvv, MO_16, do_vmulwod_s) -TRANS(vmulwod_d_w, gvec_vvv, MO_32, do_vmulwod_s) +TRANS(vmulwod_h_b, LSX, gvec_vvv, MO_8, do_vmulwod_s) +TRANS(vmulwod_w_h, LSX, gvec_vvv, MO_16, do_vmulwod_s) +TRANS(vmulwod_d_w, LSX, gvec_vvv, MO_32, do_vmulwod_s) static void gen_vmulwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -1898,9 +1906,9 @@ static void do_vmulwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmulwev_h_bu, gvec_vvv, MO_8, do_vmulwev_u) -TRANS(vmulwev_w_hu, gvec_vvv, MO_16, do_vmulwev_u) -TRANS(vmulwev_d_wu, gvec_vvv, MO_32, do_vmulwev_u) +TRANS(vmulwev_h_bu, LSX, gvec_vvv, MO_8, do_vmulwev_u) +TRANS(vmulwev_w_hu, LSX, gvec_vvv, MO_16, do_vmulwev_u) +TRANS(vmulwev_d_wu, LSX, gvec_vvv, MO_32, do_vmulwev_u) static void gen_vmulwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -1968,9 +1976,9 @@ static void do_vmulwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmulwod_h_bu, gvec_vvv, MO_8, do_vmulwod_u) -TRANS(vmulwod_w_hu, gvec_vvv, MO_16, do_vmulwod_u) -TRANS(vmulwod_d_wu, gvec_vvv, MO_32, do_vmulwod_u) +TRANS(vmulwod_h_bu, LSX, gvec_vvv, MO_8, do_vmulwod_u) +TRANS(vmulwod_w_hu, LSX, gvec_vvv, MO_16, do_vmulwod_u) +TRANS(vmulwod_d_wu, LSX, gvec_vvv, MO_32, do_vmulwod_u) static void gen_vmulwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2040,9 +2048,9 @@ static void do_vmulwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmulwev_h_bu_b, gvec_vvv, MO_8, do_vmulwev_u_s) -TRANS(vmulwev_w_hu_h, gvec_vvv, MO_16, do_vmulwev_u_s) -TRANS(vmulwev_d_wu_w, gvec_vvv, MO_32, do_vmulwev_u_s) +TRANS(vmulwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmulwev_u_s) +TRANS(vmulwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmulwev_u_s) +TRANS(vmulwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmulwev_u_s) static void gen_vmulwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2109,9 +2117,9 @@ static void do_vmulwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmulwod_h_bu_b, gvec_vvv, MO_8, do_vmulwod_u_s) -TRANS(vmulwod_w_hu_h, gvec_vvv, MO_16, do_vmulwod_u_s) -TRANS(vmulwod_d_wu_w, gvec_vvv, MO_32, do_vmulwod_u_s) +TRANS(vmulwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmulwod_u_s) +TRANS(vmulwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmulwod_u_s) +TRANS(vmulwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmulwod_u_s) static void gen_vmadd(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2182,10 +2190,10 @@ static void do_vmadd(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmadd_b, gvec_vvv, MO_8, do_vmadd) -TRANS(vmadd_h, gvec_vvv, MO_16, do_vmadd) -TRANS(vmadd_w, gvec_vvv, MO_32, do_vmadd) -TRANS(vmadd_d, gvec_vvv, MO_64, do_vmadd) +TRANS(vmadd_b, LSX, gvec_vvv, MO_8, do_vmadd) +TRANS(vmadd_h, LSX, gvec_vvv, MO_16, do_vmadd) +TRANS(vmadd_w, LSX, gvec_vvv, MO_32, do_vmadd) +TRANS(vmadd_d, LSX, gvec_vvv, MO_64, do_vmadd) static void gen_vmsub(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2256,10 +2264,10 @@ static void do_vmsub(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmsub_b, gvec_vvv, MO_8, do_vmsub) -TRANS(vmsub_h, gvec_vvv, MO_16, do_vmsub) -TRANS(vmsub_w, gvec_vvv, MO_32, do_vmsub) -TRANS(vmsub_d, gvec_vvv, MO_64, do_vmsub) +TRANS(vmsub_b, LSX, gvec_vvv, MO_8, do_vmsub) +TRANS(vmsub_h, LSX, gvec_vvv, MO_16, do_vmsub) +TRANS(vmsub_w, LSX, gvec_vvv, MO_32, do_vmsub) +TRANS(vmsub_d, LSX, gvec_vvv, MO_64, do_vmsub) static void gen_vmaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2331,15 +2339,19 @@ static void do_vmaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmaddwev_h_b, gvec_vvv, MO_8, do_vmaddwev_s) -TRANS(vmaddwev_w_h, gvec_vvv, MO_16, do_vmaddwev_s) -TRANS(vmaddwev_d_w, gvec_vvv, MO_32, do_vmaddwev_s) +TRANS(vmaddwev_h_b, LSX, gvec_vvv, MO_8, do_vmaddwev_s) +TRANS(vmaddwev_w_h, LSX, gvec_vvv, MO_16, do_vmaddwev_s) +TRANS(vmaddwev_d_w, LSX, gvec_vvv, MO_32, do_vmaddwev_s) #define VMADD_Q(NAME, FN, idx1, idx2) \ static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \ { \ TCGv_i64 rh, rl, arg1, arg2, th, tl; \ \ + if (!avail_LSX(ctx)) { \ + return false; \ + } \ + \ rh = tcg_temp_new_i64(); \ rl = tcg_temp_new_i64(); \ arg1 = tcg_temp_new_i64(); \ @@ -2435,9 +2447,9 @@ static void do_vmaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmaddwod_h_b, gvec_vvv, MO_8, do_vmaddwod_s) -TRANS(vmaddwod_w_h, gvec_vvv, MO_16, do_vmaddwod_s) -TRANS(vmaddwod_d_w, gvec_vvv, MO_32, do_vmaddwod_s) +TRANS(vmaddwod_h_b, LSX, gvec_vvv, MO_8, do_vmaddwod_s) +TRANS(vmaddwod_w_h, LSX, gvec_vvv, MO_16, do_vmaddwod_s) +TRANS(vmaddwod_d_w, LSX, gvec_vvv, MO_32, do_vmaddwod_s) static void gen_vmaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2505,9 +2517,9 @@ static void do_vmaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmaddwev_h_bu, gvec_vvv, MO_8, do_vmaddwev_u) -TRANS(vmaddwev_w_hu, gvec_vvv, MO_16, do_vmaddwev_u) -TRANS(vmaddwev_d_wu, gvec_vvv, MO_32, do_vmaddwev_u) +TRANS(vmaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwev_u) +TRANS(vmaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwev_u) +TRANS(vmaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwev_u) static void gen_vmaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2576,9 +2588,9 @@ static void do_vmaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmaddwod_h_bu, gvec_vvv, MO_8, do_vmaddwod_u) -TRANS(vmaddwod_w_hu, gvec_vvv, MO_16, do_vmaddwod_u) -TRANS(vmaddwod_d_wu, gvec_vvv, MO_32, do_vmaddwod_u) +TRANS(vmaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwod_u) +TRANS(vmaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwod_u) +TRANS(vmaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwod_u) static void gen_vmaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2649,9 +2661,9 @@ static void do_vmaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmaddwev_h_bu_b, gvec_vvv, MO_8, do_vmaddwev_u_s) -TRANS(vmaddwev_w_hu_h, gvec_vvv, MO_16, do_vmaddwev_u_s) -TRANS(vmaddwev_d_wu_w, gvec_vvv, MO_32, do_vmaddwev_u_s) +TRANS(vmaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwev_u_s) +TRANS(vmaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwev_u_s) +TRANS(vmaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwev_u_s) static void gen_vmaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2721,26 +2733,26 @@ static void do_vmaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vmaddwod_h_bu_b, gvec_vvv, MO_8, do_vmaddwod_u_s) -TRANS(vmaddwod_w_hu_h, gvec_vvv, MO_16, do_vmaddwod_u_s) -TRANS(vmaddwod_d_wu_w, gvec_vvv, MO_32, do_vmaddwod_u_s) - -TRANS(vdiv_b, gen_vvv, gen_helper_vdiv_b) -TRANS(vdiv_h, gen_vvv, gen_helper_vdiv_h) -TRANS(vdiv_w, gen_vvv, gen_helper_vdiv_w) -TRANS(vdiv_d, gen_vvv, gen_helper_vdiv_d) -TRANS(vdiv_bu, gen_vvv, gen_helper_vdiv_bu) -TRANS(vdiv_hu, gen_vvv, gen_helper_vdiv_hu) -TRANS(vdiv_wu, gen_vvv, gen_helper_vdiv_wu) -TRANS(vdiv_du, gen_vvv, gen_helper_vdiv_du) -TRANS(vmod_b, gen_vvv, gen_helper_vmod_b) -TRANS(vmod_h, gen_vvv, gen_helper_vmod_h) -TRANS(vmod_w, gen_vvv, gen_helper_vmod_w) -TRANS(vmod_d, gen_vvv, gen_helper_vmod_d) -TRANS(vmod_bu, gen_vvv, gen_helper_vmod_bu) -TRANS(vmod_hu, gen_vvv, gen_helper_vmod_hu) -TRANS(vmod_wu, gen_vvv, gen_helper_vmod_wu) -TRANS(vmod_du, gen_vvv, gen_helper_vmod_du) +TRANS(vmaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwod_u_s) +TRANS(vmaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwod_u_s) +TRANS(vmaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwod_u_s) + +TRANS(vdiv_b, LSX, gen_vvv, gen_helper_vdiv_b) +TRANS(vdiv_h, LSX, gen_vvv, gen_helper_vdiv_h) +TRANS(vdiv_w, LSX, gen_vvv, gen_helper_vdiv_w) +TRANS(vdiv_d, LSX, gen_vvv, gen_helper_vdiv_d) +TRANS(vdiv_bu, LSX, gen_vvv, gen_helper_vdiv_bu) +TRANS(vdiv_hu, LSX, gen_vvv, gen_helper_vdiv_hu) +TRANS(vdiv_wu, LSX, gen_vvv, gen_helper_vdiv_wu) +TRANS(vdiv_du, LSX, gen_vvv, gen_helper_vdiv_du) +TRANS(vmod_b, LSX, gen_vvv, gen_helper_vmod_b) +TRANS(vmod_h, LSX, gen_vvv, gen_helper_vmod_h) +TRANS(vmod_w, LSX, gen_vvv, gen_helper_vmod_w) +TRANS(vmod_d, LSX, gen_vvv, gen_helper_vmod_d) +TRANS(vmod_bu, LSX, gen_vvv, gen_helper_vmod_bu) +TRANS(vmod_hu, LSX, gen_vvv, gen_helper_vmod_hu) +TRANS(vmod_wu, LSX, gen_vvv, gen_helper_vmod_wu) +TRANS(vmod_du, LSX, gen_vvv, gen_helper_vmod_du) static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max) { @@ -2789,10 +2801,10 @@ static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_constant_i64((1ll<< imm) -1), &op[vece]); } -TRANS(vsat_b, gvec_vv_i, MO_8, do_vsat_s) -TRANS(vsat_h, gvec_vv_i, MO_16, do_vsat_s) -TRANS(vsat_w, gvec_vv_i, MO_32, do_vsat_s) -TRANS(vsat_d, gvec_vv_i, MO_64, do_vsat_s) +TRANS(vsat_b, LSX, gvec_vv_i, MO_8, do_vsat_s) +TRANS(vsat_h, LSX, gvec_vv_i, MO_16, do_vsat_s) +TRANS(vsat_w, LSX, gvec_vv_i, MO_32, do_vsat_s) +TRANS(vsat_d, LSX, gvec_vv_i, MO_64, do_vsat_s) static void gen_vsat_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max) { @@ -2838,19 +2850,19 @@ static void do_vsat_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_constant_i64(max), &op[vece]); } -TRANS(vsat_bu, gvec_vv_i, MO_8, do_vsat_u) -TRANS(vsat_hu, gvec_vv_i, MO_16, do_vsat_u) -TRANS(vsat_wu, gvec_vv_i, MO_32, do_vsat_u) -TRANS(vsat_du, gvec_vv_i, MO_64, do_vsat_u) +TRANS(vsat_bu, LSX, gvec_vv_i, MO_8, do_vsat_u) +TRANS(vsat_hu, LSX, gvec_vv_i, MO_16, do_vsat_u) +TRANS(vsat_wu, LSX, gvec_vv_i, MO_32, do_vsat_u) +TRANS(vsat_du, LSX, gvec_vv_i, MO_64, do_vsat_u) -TRANS(vexth_h_b, gen_vv, gen_helper_vexth_h_b) -TRANS(vexth_w_h, gen_vv, gen_helper_vexth_w_h) -TRANS(vexth_d_w, gen_vv, gen_helper_vexth_d_w) -TRANS(vexth_q_d, gen_vv, gen_helper_vexth_q_d) -TRANS(vexth_hu_bu, gen_vv, gen_helper_vexth_hu_bu) -TRANS(vexth_wu_hu, gen_vv, gen_helper_vexth_wu_hu) -TRANS(vexth_du_wu, gen_vv, gen_helper_vexth_du_wu) -TRANS(vexth_qu_du, gen_vv, gen_helper_vexth_qu_du) +TRANS(vexth_h_b, LSX, gen_vv, gen_helper_vexth_h_b) +TRANS(vexth_w_h, LSX, gen_vv, gen_helper_vexth_w_h) +TRANS(vexth_d_w, LSX, gen_vv, gen_helper_vexth_d_w) +TRANS(vexth_q_d, LSX, gen_vv, gen_helper_vexth_q_d) +TRANS(vexth_hu_bu, LSX, gen_vv, gen_helper_vexth_hu_bu) +TRANS(vexth_wu_hu, LSX, gen_vv, gen_helper_vexth_wu_hu) +TRANS(vexth_du_wu, LSX, gen_vv, gen_helper_vexth_du_wu) +TRANS(vexth_qu_du, LSX, gen_vv, gen_helper_vexth_qu_du) static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b) { @@ -2900,17 +2912,17 @@ static void do_vsigncov(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vsigncov_b, gvec_vvv, MO_8, do_vsigncov) -TRANS(vsigncov_h, gvec_vvv, MO_16, do_vsigncov) -TRANS(vsigncov_w, gvec_vvv, MO_32, do_vsigncov) -TRANS(vsigncov_d, gvec_vvv, MO_64, do_vsigncov) +TRANS(vsigncov_b, LSX, gvec_vvv, MO_8, do_vsigncov) +TRANS(vsigncov_h, LSX, gvec_vvv, MO_16, do_vsigncov) +TRANS(vsigncov_w, LSX, gvec_vvv, MO_32, do_vsigncov) +TRANS(vsigncov_d, LSX, gvec_vvv, MO_64, do_vsigncov) -TRANS(vmskltz_b, gen_vv, gen_helper_vmskltz_b) -TRANS(vmskltz_h, gen_vv, gen_helper_vmskltz_h) -TRANS(vmskltz_w, gen_vv, gen_helper_vmskltz_w) -TRANS(vmskltz_d, gen_vv, gen_helper_vmskltz_d) -TRANS(vmskgez_b, gen_vv, gen_helper_vmskgez_b) -TRANS(vmsknz_b, gen_vv, gen_helper_vmsknz_b) +TRANS(vmskltz_b, LSX, gen_vv, gen_helper_vmskltz_b) +TRANS(vmskltz_h, LSX, gen_vv, gen_helper_vmskltz_h) +TRANS(vmskltz_w, LSX, gen_vv, gen_helper_vmskltz_w) +TRANS(vmskltz_d, LSX, gen_vv, gen_helper_vmskltz_d) +TRANS(vmskgez_b, LSX, gen_vv, gen_helper_vmskgez_b) +TRANS(vmsknz_b, LSX, gen_vv, gen_helper_vmsknz_b) #define EXPAND_BYTE(bit) ((uint64_t)(bit ? 0xff : 0)) @@ -3032,6 +3044,11 @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a) { int sel, vece; uint64_t value; + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; sel = (a->imm >> 12) & 0x1; @@ -3049,15 +3066,19 @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a) return true; } -TRANS(vand_v, gvec_vvv, MO_64, tcg_gen_gvec_and) -TRANS(vor_v, gvec_vvv, MO_64, tcg_gen_gvec_or) -TRANS(vxor_v, gvec_vvv, MO_64, tcg_gen_gvec_xor) -TRANS(vnor_v, gvec_vvv, MO_64, tcg_gen_gvec_nor) +TRANS(vand_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_and) +TRANS(vor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_or) +TRANS(vxor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_xor) +TRANS(vnor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_nor) static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a) { uint32_t vd_ofs, vj_ofs, vk_ofs; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; vd_ofs = vec_full_offset(a->vd); @@ -3067,10 +3088,10 @@ static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a) tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, 16, ctx->vl/8); return true; } -TRANS(vorn_v, gvec_vvv, MO_64, tcg_gen_gvec_orc) -TRANS(vandi_b, gvec_vv_i, MO_8, tcg_gen_gvec_andi) -TRANS(vori_b, gvec_vv_i, MO_8, tcg_gen_gvec_ori) -TRANS(vxori_b, gvec_vv_i, MO_8, tcg_gen_gvec_xori) +TRANS(vorn_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_orc) +TRANS(vandi_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_andi) +TRANS(vori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_ori) +TRANS(vxori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_xori) static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm) { @@ -3103,176 +3124,176 @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op); } -TRANS(vnori_b, gvec_vv_i, MO_8, do_vnori_b) - -TRANS(vsll_b, gvec_vvv, MO_8, tcg_gen_gvec_shlv) -TRANS(vsll_h, gvec_vvv, MO_16, tcg_gen_gvec_shlv) -TRANS(vsll_w, gvec_vvv, MO_32, tcg_gen_gvec_shlv) -TRANS(vsll_d, gvec_vvv, MO_64, tcg_gen_gvec_shlv) -TRANS(vslli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shli) -TRANS(vslli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shli) -TRANS(vslli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shli) -TRANS(vslli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shli) - -TRANS(vsrl_b, gvec_vvv, MO_8, tcg_gen_gvec_shrv) -TRANS(vsrl_h, gvec_vvv, MO_16, tcg_gen_gvec_shrv) -TRANS(vsrl_w, gvec_vvv, MO_32, tcg_gen_gvec_shrv) -TRANS(vsrl_d, gvec_vvv, MO_64, tcg_gen_gvec_shrv) -TRANS(vsrli_b, gvec_vv_i, MO_8, tcg_gen_gvec_shri) -TRANS(vsrli_h, gvec_vv_i, MO_16, tcg_gen_gvec_shri) -TRANS(vsrli_w, gvec_vv_i, MO_32, tcg_gen_gvec_shri) -TRANS(vsrli_d, gvec_vv_i, MO_64, tcg_gen_gvec_shri) - -TRANS(vsra_b, gvec_vvv, MO_8, tcg_gen_gvec_sarv) -TRANS(vsra_h, gvec_vvv, MO_16, tcg_gen_gvec_sarv) -TRANS(vsra_w, gvec_vvv, MO_32, tcg_gen_gvec_sarv) -TRANS(vsra_d, gvec_vvv, MO_64, tcg_gen_gvec_sarv) -TRANS(vsrai_b, gvec_vv_i, MO_8, tcg_gen_gvec_sari) -TRANS(vsrai_h, gvec_vv_i, MO_16, tcg_gen_gvec_sari) -TRANS(vsrai_w, gvec_vv_i, MO_32, tcg_gen_gvec_sari) -TRANS(vsrai_d, gvec_vv_i, MO_64, tcg_gen_gvec_sari) - -TRANS(vrotr_b, gvec_vvv, MO_8, tcg_gen_gvec_rotrv) -TRANS(vrotr_h, gvec_vvv, MO_16, tcg_gen_gvec_rotrv) -TRANS(vrotr_w, gvec_vvv, MO_32, tcg_gen_gvec_rotrv) -TRANS(vrotr_d, gvec_vvv, MO_64, tcg_gen_gvec_rotrv) -TRANS(vrotri_b, gvec_vv_i, MO_8, tcg_gen_gvec_rotri) -TRANS(vrotri_h, gvec_vv_i, MO_16, tcg_gen_gvec_rotri) -TRANS(vrotri_w, gvec_vv_i, MO_32, tcg_gen_gvec_rotri) -TRANS(vrotri_d, gvec_vv_i, MO_64, tcg_gen_gvec_rotri) - -TRANS(vsllwil_h_b, gen_vv_i, gen_helper_vsllwil_h_b) -TRANS(vsllwil_w_h, gen_vv_i, gen_helper_vsllwil_w_h) -TRANS(vsllwil_d_w, gen_vv_i, gen_helper_vsllwil_d_w) -TRANS(vextl_q_d, gen_vv, gen_helper_vextl_q_d) -TRANS(vsllwil_hu_bu, gen_vv_i, gen_helper_vsllwil_hu_bu) -TRANS(vsllwil_wu_hu, gen_vv_i, gen_helper_vsllwil_wu_hu) -TRANS(vsllwil_du_wu, gen_vv_i, gen_helper_vsllwil_du_wu) -TRANS(vextl_qu_du, gen_vv, gen_helper_vextl_qu_du) - -TRANS(vsrlr_b, gen_vvv, gen_helper_vsrlr_b) -TRANS(vsrlr_h, gen_vvv, gen_helper_vsrlr_h) -TRANS(vsrlr_w, gen_vvv, gen_helper_vsrlr_w) -TRANS(vsrlr_d, gen_vvv, gen_helper_vsrlr_d) -TRANS(vsrlri_b, gen_vv_i, gen_helper_vsrlri_b) -TRANS(vsrlri_h, gen_vv_i, gen_helper_vsrlri_h) -TRANS(vsrlri_w, gen_vv_i, gen_helper_vsrlri_w) -TRANS(vsrlri_d, gen_vv_i, gen_helper_vsrlri_d) - -TRANS(vsrar_b, gen_vvv, gen_helper_vsrar_b) -TRANS(vsrar_h, gen_vvv, gen_helper_vsrar_h) -TRANS(vsrar_w, gen_vvv, gen_helper_vsrar_w) -TRANS(vsrar_d, gen_vvv, gen_helper_vsrar_d) -TRANS(vsrari_b, gen_vv_i, gen_helper_vsrari_b) -TRANS(vsrari_h, gen_vv_i, gen_helper_vsrari_h) -TRANS(vsrari_w, gen_vv_i, gen_helper_vsrari_w) -TRANS(vsrari_d, gen_vv_i, gen_helper_vsrari_d) - -TRANS(vsrln_b_h, gen_vvv, gen_helper_vsrln_b_h) -TRANS(vsrln_h_w, gen_vvv, gen_helper_vsrln_h_w) -TRANS(vsrln_w_d, gen_vvv, gen_helper_vsrln_w_d) -TRANS(vsran_b_h, gen_vvv, gen_helper_vsran_b_h) -TRANS(vsran_h_w, gen_vvv, gen_helper_vsran_h_w) -TRANS(vsran_w_d, gen_vvv, gen_helper_vsran_w_d) - -TRANS(vsrlni_b_h, gen_vv_i, gen_helper_vsrlni_b_h) -TRANS(vsrlni_h_w, gen_vv_i, gen_helper_vsrlni_h_w) -TRANS(vsrlni_w_d, gen_vv_i, gen_helper_vsrlni_w_d) -TRANS(vsrlni_d_q, gen_vv_i, gen_helper_vsrlni_d_q) -TRANS(vsrani_b_h, gen_vv_i, gen_helper_vsrani_b_h) -TRANS(vsrani_h_w, gen_vv_i, gen_helper_vsrani_h_w) -TRANS(vsrani_w_d, gen_vv_i, gen_helper_vsrani_w_d) -TRANS(vsrani_d_q, gen_vv_i, gen_helper_vsrani_d_q) - -TRANS(vsrlrn_b_h, gen_vvv, gen_helper_vsrlrn_b_h) -TRANS(vsrlrn_h_w, gen_vvv, gen_helper_vsrlrn_h_w) -TRANS(vsrlrn_w_d, gen_vvv, gen_helper_vsrlrn_w_d) -TRANS(vsrarn_b_h, gen_vvv, gen_helper_vsrarn_b_h) -TRANS(vsrarn_h_w, gen_vvv, gen_helper_vsrarn_h_w) -TRANS(vsrarn_w_d, gen_vvv, gen_helper_vsrarn_w_d) - -TRANS(vsrlrni_b_h, gen_vv_i, gen_helper_vsrlrni_b_h) -TRANS(vsrlrni_h_w, gen_vv_i, gen_helper_vsrlrni_h_w) -TRANS(vsrlrni_w_d, gen_vv_i, gen_helper_vsrlrni_w_d) -TRANS(vsrlrni_d_q, gen_vv_i, gen_helper_vsrlrni_d_q) -TRANS(vsrarni_b_h, gen_vv_i, gen_helper_vsrarni_b_h) -TRANS(vsrarni_h_w, gen_vv_i, gen_helper_vsrarni_h_w) -TRANS(vsrarni_w_d, gen_vv_i, gen_helper_vsrarni_w_d) -TRANS(vsrarni_d_q, gen_vv_i, gen_helper_vsrarni_d_q) - -TRANS(vssrln_b_h, gen_vvv, gen_helper_vssrln_b_h) -TRANS(vssrln_h_w, gen_vvv, gen_helper_vssrln_h_w) -TRANS(vssrln_w_d, gen_vvv, gen_helper_vssrln_w_d) -TRANS(vssran_b_h, gen_vvv, gen_helper_vssran_b_h) -TRANS(vssran_h_w, gen_vvv, gen_helper_vssran_h_w) -TRANS(vssran_w_d, gen_vvv, gen_helper_vssran_w_d) -TRANS(vssrln_bu_h, gen_vvv, gen_helper_vssrln_bu_h) -TRANS(vssrln_hu_w, gen_vvv, gen_helper_vssrln_hu_w) -TRANS(vssrln_wu_d, gen_vvv, gen_helper_vssrln_wu_d) -TRANS(vssran_bu_h, gen_vvv, gen_helper_vssran_bu_h) -TRANS(vssran_hu_w, gen_vvv, gen_helper_vssran_hu_w) -TRANS(vssran_wu_d, gen_vvv, gen_helper_vssran_wu_d) - -TRANS(vssrlni_b_h, gen_vv_i, gen_helper_vssrlni_b_h) -TRANS(vssrlni_h_w, gen_vv_i, gen_helper_vssrlni_h_w) -TRANS(vssrlni_w_d, gen_vv_i, gen_helper_vssrlni_w_d) -TRANS(vssrlni_d_q, gen_vv_i, gen_helper_vssrlni_d_q) -TRANS(vssrani_b_h, gen_vv_i, gen_helper_vssrani_b_h) -TRANS(vssrani_h_w, gen_vv_i, gen_helper_vssrani_h_w) -TRANS(vssrani_w_d, gen_vv_i, gen_helper_vssrani_w_d) -TRANS(vssrani_d_q, gen_vv_i, gen_helper_vssrani_d_q) -TRANS(vssrlni_bu_h, gen_vv_i, gen_helper_vssrlni_bu_h) -TRANS(vssrlni_hu_w, gen_vv_i, gen_helper_vssrlni_hu_w) -TRANS(vssrlni_wu_d, gen_vv_i, gen_helper_vssrlni_wu_d) -TRANS(vssrlni_du_q, gen_vv_i, gen_helper_vssrlni_du_q) -TRANS(vssrani_bu_h, gen_vv_i, gen_helper_vssrani_bu_h) -TRANS(vssrani_hu_w, gen_vv_i, gen_helper_vssrani_hu_w) -TRANS(vssrani_wu_d, gen_vv_i, gen_helper_vssrani_wu_d) -TRANS(vssrani_du_q, gen_vv_i, gen_helper_vssrani_du_q) - -TRANS(vssrlrn_b_h, gen_vvv, gen_helper_vssrlrn_b_h) -TRANS(vssrlrn_h_w, gen_vvv, gen_helper_vssrlrn_h_w) -TRANS(vssrlrn_w_d, gen_vvv, gen_helper_vssrlrn_w_d) -TRANS(vssrarn_b_h, gen_vvv, gen_helper_vssrarn_b_h) -TRANS(vssrarn_h_w, gen_vvv, gen_helper_vssrarn_h_w) -TRANS(vssrarn_w_d, gen_vvv, gen_helper_vssrarn_w_d) -TRANS(vssrlrn_bu_h, gen_vvv, gen_helper_vssrlrn_bu_h) -TRANS(vssrlrn_hu_w, gen_vvv, gen_helper_vssrlrn_hu_w) -TRANS(vssrlrn_wu_d, gen_vvv, gen_helper_vssrlrn_wu_d) -TRANS(vssrarn_bu_h, gen_vvv, gen_helper_vssrarn_bu_h) -TRANS(vssrarn_hu_w, gen_vvv, gen_helper_vssrarn_hu_w) -TRANS(vssrarn_wu_d, gen_vvv, gen_helper_vssrarn_wu_d) - -TRANS(vssrlrni_b_h, gen_vv_i, gen_helper_vssrlrni_b_h) -TRANS(vssrlrni_h_w, gen_vv_i, gen_helper_vssrlrni_h_w) -TRANS(vssrlrni_w_d, gen_vv_i, gen_helper_vssrlrni_w_d) -TRANS(vssrlrni_d_q, gen_vv_i, gen_helper_vssrlrni_d_q) -TRANS(vssrarni_b_h, gen_vv_i, gen_helper_vssrarni_b_h) -TRANS(vssrarni_h_w, gen_vv_i, gen_helper_vssrarni_h_w) -TRANS(vssrarni_w_d, gen_vv_i, gen_helper_vssrarni_w_d) -TRANS(vssrarni_d_q, gen_vv_i, gen_helper_vssrarni_d_q) -TRANS(vssrlrni_bu_h, gen_vv_i, gen_helper_vssrlrni_bu_h) -TRANS(vssrlrni_hu_w, gen_vv_i, gen_helper_vssrlrni_hu_w) -TRANS(vssrlrni_wu_d, gen_vv_i, gen_helper_vssrlrni_wu_d) -TRANS(vssrlrni_du_q, gen_vv_i, gen_helper_vssrlrni_du_q) -TRANS(vssrarni_bu_h, gen_vv_i, gen_helper_vssrarni_bu_h) -TRANS(vssrarni_hu_w, gen_vv_i, gen_helper_vssrarni_hu_w) -TRANS(vssrarni_wu_d, gen_vv_i, gen_helper_vssrarni_wu_d) -TRANS(vssrarni_du_q, gen_vv_i, gen_helper_vssrarni_du_q) - -TRANS(vclo_b, gen_vv, gen_helper_vclo_b) -TRANS(vclo_h, gen_vv, gen_helper_vclo_h) -TRANS(vclo_w, gen_vv, gen_helper_vclo_w) -TRANS(vclo_d, gen_vv, gen_helper_vclo_d) -TRANS(vclz_b, gen_vv, gen_helper_vclz_b) -TRANS(vclz_h, gen_vv, gen_helper_vclz_h) -TRANS(vclz_w, gen_vv, gen_helper_vclz_w) -TRANS(vclz_d, gen_vv, gen_helper_vclz_d) - -TRANS(vpcnt_b, gen_vv, gen_helper_vpcnt_b) -TRANS(vpcnt_h, gen_vv, gen_helper_vpcnt_h) -TRANS(vpcnt_w, gen_vv, gen_helper_vpcnt_w) -TRANS(vpcnt_d, gen_vv, gen_helper_vpcnt_d) +TRANS(vnori_b, LSX, gvec_vv_i, MO_8, do_vnori_b) + +TRANS(vsll_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shlv) +TRANS(vsll_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shlv) +TRANS(vsll_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_shlv) +TRANS(vsll_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_shlv) +TRANS(vslli_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_shli) +TRANS(vslli_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_shli) +TRANS(vslli_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_shli) +TRANS(vslli_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_shli) + +TRANS(vsrl_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shrv) +TRANS(vsrl_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shrv) +TRANS(vsrl_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_shrv) +TRANS(vsrl_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_shrv) +TRANS(vsrli_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_shri) +TRANS(vsrli_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_shri) +TRANS(vsrli_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_shri) +TRANS(vsrli_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_shri) + +TRANS(vsra_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sarv) +TRANS(vsra_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sarv) +TRANS(vsra_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sarv) +TRANS(vsra_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sarv) +TRANS(vsrai_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_sari) +TRANS(vsrai_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_sari) +TRANS(vsrai_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_sari) +TRANS(vsrai_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_sari) + +TRANS(vrotr_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_rotrv) +TRANS(vrotr_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_rotrv) +TRANS(vrotr_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_rotrv) +TRANS(vrotr_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_rotrv) +TRANS(vrotri_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_rotri) +TRANS(vrotri_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_rotri) +TRANS(vrotri_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_rotri) +TRANS(vrotri_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_rotri) + +TRANS(vsllwil_h_b, LSX, gen_vv_i, gen_helper_vsllwil_h_b) +TRANS(vsllwil_w_h, LSX, gen_vv_i, gen_helper_vsllwil_w_h) +TRANS(vsllwil_d_w, LSX, gen_vv_i, gen_helper_vsllwil_d_w) +TRANS(vextl_q_d, LSX, gen_vv, gen_helper_vextl_q_d) +TRANS(vsllwil_hu_bu, LSX, gen_vv_i, gen_helper_vsllwil_hu_bu) +TRANS(vsllwil_wu_hu, LSX, gen_vv_i, gen_helper_vsllwil_wu_hu) +TRANS(vsllwil_du_wu, LSX, gen_vv_i, gen_helper_vsllwil_du_wu) +TRANS(vextl_qu_du, LSX, gen_vv, gen_helper_vextl_qu_du) + +TRANS(vsrlr_b, LSX, gen_vvv, gen_helper_vsrlr_b) +TRANS(vsrlr_h, LSX, gen_vvv, gen_helper_vsrlr_h) +TRANS(vsrlr_w, LSX, gen_vvv, gen_helper_vsrlr_w) +TRANS(vsrlr_d, LSX, gen_vvv, gen_helper_vsrlr_d) +TRANS(vsrlri_b, LSX, gen_vv_i, gen_helper_vsrlri_b) +TRANS(vsrlri_h, LSX, gen_vv_i, gen_helper_vsrlri_h) +TRANS(vsrlri_w, LSX, gen_vv_i, gen_helper_vsrlri_w) +TRANS(vsrlri_d, LSX, gen_vv_i, gen_helper_vsrlri_d) + +TRANS(vsrar_b, LSX, gen_vvv, gen_helper_vsrar_b) +TRANS(vsrar_h, LSX, gen_vvv, gen_helper_vsrar_h) +TRANS(vsrar_w, LSX, gen_vvv, gen_helper_vsrar_w) +TRANS(vsrar_d, LSX, gen_vvv, gen_helper_vsrar_d) +TRANS(vsrari_b, LSX, gen_vv_i, gen_helper_vsrari_b) +TRANS(vsrari_h, LSX, gen_vv_i, gen_helper_vsrari_h) +TRANS(vsrari_w, LSX, gen_vv_i, gen_helper_vsrari_w) +TRANS(vsrari_d, LSX, gen_vv_i, gen_helper_vsrari_d) + +TRANS(vsrln_b_h, LSX, gen_vvv, gen_helper_vsrln_b_h) +TRANS(vsrln_h_w, LSX, gen_vvv, gen_helper_vsrln_h_w) +TRANS(vsrln_w_d, LSX, gen_vvv, gen_helper_vsrln_w_d) +TRANS(vsran_b_h, LSX, gen_vvv, gen_helper_vsran_b_h) +TRANS(vsran_h_w, LSX, gen_vvv, gen_helper_vsran_h_w) +TRANS(vsran_w_d, LSX, gen_vvv, gen_helper_vsran_w_d) + +TRANS(vsrlni_b_h, LSX, gen_vv_i, gen_helper_vsrlni_b_h) +TRANS(vsrlni_h_w, LSX, gen_vv_i, gen_helper_vsrlni_h_w) +TRANS(vsrlni_w_d, LSX, gen_vv_i, gen_helper_vsrlni_w_d) +TRANS(vsrlni_d_q, LSX, gen_vv_i, gen_helper_vsrlni_d_q) +TRANS(vsrani_b_h, LSX, gen_vv_i, gen_helper_vsrani_b_h) +TRANS(vsrani_h_w, LSX, gen_vv_i, gen_helper_vsrani_h_w) +TRANS(vsrani_w_d, LSX, gen_vv_i, gen_helper_vsrani_w_d) +TRANS(vsrani_d_q, LSX, gen_vv_i, gen_helper_vsrani_d_q) + +TRANS(vsrlrn_b_h, LSX, gen_vvv, gen_helper_vsrlrn_b_h) +TRANS(vsrlrn_h_w, LSX, gen_vvv, gen_helper_vsrlrn_h_w) +TRANS(vsrlrn_w_d, LSX, gen_vvv, gen_helper_vsrlrn_w_d) +TRANS(vsrarn_b_h, LSX, gen_vvv, gen_helper_vsrarn_b_h) +TRANS(vsrarn_h_w, LSX, gen_vvv, gen_helper_vsrarn_h_w) +TRANS(vsrarn_w_d, LSX, gen_vvv, gen_helper_vsrarn_w_d) + +TRANS(vsrlrni_b_h, LSX, gen_vv_i, gen_helper_vsrlrni_b_h) +TRANS(vsrlrni_h_w, LSX, gen_vv_i, gen_helper_vsrlrni_h_w) +TRANS(vsrlrni_w_d, LSX, gen_vv_i, gen_helper_vsrlrni_w_d) +TRANS(vsrlrni_d_q, LSX, gen_vv_i, gen_helper_vsrlrni_d_q) +TRANS(vsrarni_b_h, LSX, gen_vv_i, gen_helper_vsrarni_b_h) +TRANS(vsrarni_h_w, LSX, gen_vv_i, gen_helper_vsrarni_h_w) +TRANS(vsrarni_w_d, LSX, gen_vv_i, gen_helper_vsrarni_w_d) +TRANS(vsrarni_d_q, LSX, gen_vv_i, gen_helper_vsrarni_d_q) + +TRANS(vssrln_b_h, LSX, gen_vvv, gen_helper_vssrln_b_h) +TRANS(vssrln_h_w, LSX, gen_vvv, gen_helper_vssrln_h_w) +TRANS(vssrln_w_d, LSX, gen_vvv, gen_helper_vssrln_w_d) +TRANS(vssran_b_h, LSX, gen_vvv, gen_helper_vssran_b_h) +TRANS(vssran_h_w, LSX, gen_vvv, gen_helper_vssran_h_w) +TRANS(vssran_w_d, LSX, gen_vvv, gen_helper_vssran_w_d) +TRANS(vssrln_bu_h, LSX, gen_vvv, gen_helper_vssrln_bu_h) +TRANS(vssrln_hu_w, LSX, gen_vvv, gen_helper_vssrln_hu_w) +TRANS(vssrln_wu_d, LSX, gen_vvv, gen_helper_vssrln_wu_d) +TRANS(vssran_bu_h, LSX, gen_vvv, gen_helper_vssran_bu_h) +TRANS(vssran_hu_w, LSX, gen_vvv, gen_helper_vssran_hu_w) +TRANS(vssran_wu_d, LSX, gen_vvv, gen_helper_vssran_wu_d) + +TRANS(vssrlni_b_h, LSX, gen_vv_i, gen_helper_vssrlni_b_h) +TRANS(vssrlni_h_w, LSX, gen_vv_i, gen_helper_vssrlni_h_w) +TRANS(vssrlni_w_d, LSX, gen_vv_i, gen_helper_vssrlni_w_d) +TRANS(vssrlni_d_q, LSX, gen_vv_i, gen_helper_vssrlni_d_q) +TRANS(vssrani_b_h, LSX, gen_vv_i, gen_helper_vssrani_b_h) +TRANS(vssrani_h_w, LSX, gen_vv_i, gen_helper_vssrani_h_w) +TRANS(vssrani_w_d, LSX, gen_vv_i, gen_helper_vssrani_w_d) +TRANS(vssrani_d_q, LSX, gen_vv_i, gen_helper_vssrani_d_q) +TRANS(vssrlni_bu_h, LSX, gen_vv_i, gen_helper_vssrlni_bu_h) +TRANS(vssrlni_hu_w, LSX, gen_vv_i, gen_helper_vssrlni_hu_w) +TRANS(vssrlni_wu_d, LSX, gen_vv_i, gen_helper_vssrlni_wu_d) +TRANS(vssrlni_du_q, LSX, gen_vv_i, gen_helper_vssrlni_du_q) +TRANS(vssrani_bu_h, LSX, gen_vv_i, gen_helper_vssrani_bu_h) +TRANS(vssrani_hu_w, LSX, gen_vv_i, gen_helper_vssrani_hu_w) +TRANS(vssrani_wu_d, LSX, gen_vv_i, gen_helper_vssrani_wu_d) +TRANS(vssrani_du_q, LSX, gen_vv_i, gen_helper_vssrani_du_q) + +TRANS(vssrlrn_b_h, LSX, gen_vvv, gen_helper_vssrlrn_b_h) +TRANS(vssrlrn_h_w, LSX, gen_vvv, gen_helper_vssrlrn_h_w) +TRANS(vssrlrn_w_d, LSX, gen_vvv, gen_helper_vssrlrn_w_d) +TRANS(vssrarn_b_h, LSX, gen_vvv, gen_helper_vssrarn_b_h) +TRANS(vssrarn_h_w, LSX, gen_vvv, gen_helper_vssrarn_h_w) +TRANS(vssrarn_w_d, LSX, gen_vvv, gen_helper_vssrarn_w_d) +TRANS(vssrlrn_bu_h, LSX, gen_vvv, gen_helper_vssrlrn_bu_h) +TRANS(vssrlrn_hu_w, LSX, gen_vvv, gen_helper_vssrlrn_hu_w) +TRANS(vssrlrn_wu_d, LSX, gen_vvv, gen_helper_vssrlrn_wu_d) +TRANS(vssrarn_bu_h, LSX, gen_vvv, gen_helper_vssrarn_bu_h) +TRANS(vssrarn_hu_w, LSX, gen_vvv, gen_helper_vssrarn_hu_w) +TRANS(vssrarn_wu_d, LSX, gen_vvv, gen_helper_vssrarn_wu_d) + +TRANS(vssrlrni_b_h, LSX, gen_vv_i, gen_helper_vssrlrni_b_h) +TRANS(vssrlrni_h_w, LSX, gen_vv_i, gen_helper_vssrlrni_h_w) +TRANS(vssrlrni_w_d, LSX, gen_vv_i, gen_helper_vssrlrni_w_d) +TRANS(vssrlrni_d_q, LSX, gen_vv_i, gen_helper_vssrlrni_d_q) +TRANS(vssrarni_b_h, LSX, gen_vv_i, gen_helper_vssrarni_b_h) +TRANS(vssrarni_h_w, LSX, gen_vv_i, gen_helper_vssrarni_h_w) +TRANS(vssrarni_w_d, LSX, gen_vv_i, gen_helper_vssrarni_w_d) +TRANS(vssrarni_d_q, LSX, gen_vv_i, gen_helper_vssrarni_d_q) +TRANS(vssrlrni_bu_h, LSX, gen_vv_i, gen_helper_vssrlrni_bu_h) +TRANS(vssrlrni_hu_w, LSX, gen_vv_i, gen_helper_vssrlrni_hu_w) +TRANS(vssrlrni_wu_d, LSX, gen_vv_i, gen_helper_vssrlrni_wu_d) +TRANS(vssrlrni_du_q, LSX, gen_vv_i, gen_helper_vssrlrni_du_q) +TRANS(vssrarni_bu_h, LSX, gen_vv_i, gen_helper_vssrarni_bu_h) +TRANS(vssrarni_hu_w, LSX, gen_vv_i, gen_helper_vssrarni_hu_w) +TRANS(vssrarni_wu_d, LSX, gen_vv_i, gen_helper_vssrarni_wu_d) +TRANS(vssrarni_du_q, LSX, gen_vv_i, gen_helper_vssrarni_du_q) + +TRANS(vclo_b, LSX, gen_vv, gen_helper_vclo_b) +TRANS(vclo_h, LSX, gen_vv, gen_helper_vclo_h) +TRANS(vclo_w, LSX, gen_vv, gen_helper_vclo_w) +TRANS(vclo_d, LSX, gen_vv, gen_helper_vclo_d) +TRANS(vclz_b, LSX, gen_vv, gen_helper_vclz_b) +TRANS(vclz_h, LSX, gen_vv, gen_helper_vclz_h) +TRANS(vclz_w, LSX, gen_vv, gen_helper_vclz_w) +TRANS(vclz_d, LSX, gen_vv, gen_helper_vclz_d) + +TRANS(vpcnt_b, LSX, gen_vv, gen_helper_vpcnt_b) +TRANS(vpcnt_h, LSX, gen_vv, gen_helper_vpcnt_h) +TRANS(vpcnt_w, LSX, gen_vv, gen_helper_vpcnt_w) +TRANS(vpcnt_d, LSX, gen_vv, gen_helper_vpcnt_d) static void do_vbit(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b, void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec)) @@ -3340,10 +3361,10 @@ static void do_vbitclr(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vbitclr_b, gvec_vvv, MO_8, do_vbitclr) -TRANS(vbitclr_h, gvec_vvv, MO_16, do_vbitclr) -TRANS(vbitclr_w, gvec_vvv, MO_32, do_vbitclr) -TRANS(vbitclr_d, gvec_vvv, MO_64, do_vbitclr) +TRANS(vbitclr_b, LSX, gvec_vvv, MO_8, do_vbitclr) +TRANS(vbitclr_h, LSX, gvec_vvv, MO_16, do_vbitclr) +TRANS(vbitclr_w, LSX, gvec_vvv, MO_32, do_vbitclr) +TRANS(vbitclr_d, LSX, gvec_vvv, MO_64, do_vbitclr) static void do_vbiti(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm, void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec)) @@ -3410,10 +3431,10 @@ static void do_vbitclri(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); } -TRANS(vbitclri_b, gvec_vv_i, MO_8, do_vbitclri) -TRANS(vbitclri_h, gvec_vv_i, MO_16, do_vbitclri) -TRANS(vbitclri_w, gvec_vv_i, MO_32, do_vbitclri) -TRANS(vbitclri_d, gvec_vv_i, MO_64, do_vbitclri) +TRANS(vbitclri_b, LSX, gvec_vv_i, MO_8, do_vbitclri) +TRANS(vbitclri_h, LSX, gvec_vv_i, MO_16, do_vbitclri) +TRANS(vbitclri_w, LSX, gvec_vv_i, MO_32, do_vbitclri) +TRANS(vbitclri_d, LSX, gvec_vv_i, MO_64, do_vbitclri) static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz) @@ -3451,10 +3472,10 @@ static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vbitset_b, gvec_vvv, MO_8, do_vbitset) -TRANS(vbitset_h, gvec_vvv, MO_16, do_vbitset) -TRANS(vbitset_w, gvec_vvv, MO_32, do_vbitset) -TRANS(vbitset_d, gvec_vvv, MO_64, do_vbitset) +TRANS(vbitset_b, LSX, gvec_vvv, MO_8, do_vbitset) +TRANS(vbitset_h, LSX, gvec_vvv, MO_16, do_vbitset) +TRANS(vbitset_w, LSX, gvec_vvv, MO_32, do_vbitset) +TRANS(vbitset_d, LSX, gvec_vvv, MO_64, do_vbitset) static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, int64_t imm, uint32_t oprsz, uint32_t maxsz) @@ -3492,10 +3513,10 @@ static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); } -TRANS(vbitseti_b, gvec_vv_i, MO_8, do_vbitseti) -TRANS(vbitseti_h, gvec_vv_i, MO_16, do_vbitseti) -TRANS(vbitseti_w, gvec_vv_i, MO_32, do_vbitseti) -TRANS(vbitseti_d, gvec_vv_i, MO_64, do_vbitseti) +TRANS(vbitseti_b, LSX, gvec_vv_i, MO_8, do_vbitseti) +TRANS(vbitseti_h, LSX, gvec_vv_i, MO_16, do_vbitseti) +TRANS(vbitseti_w, LSX, gvec_vv_i, MO_32, do_vbitseti) +TRANS(vbitseti_d, LSX, gvec_vv_i, MO_64, do_vbitseti) static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz) @@ -3533,10 +3554,10 @@ static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]); } -TRANS(vbitrev_b, gvec_vvv, MO_8, do_vbitrev) -TRANS(vbitrev_h, gvec_vvv, MO_16, do_vbitrev) -TRANS(vbitrev_w, gvec_vvv, MO_32, do_vbitrev) -TRANS(vbitrev_d, gvec_vvv, MO_64, do_vbitrev) +TRANS(vbitrev_b, LSX, gvec_vvv, MO_8, do_vbitrev) +TRANS(vbitrev_h, LSX, gvec_vvv, MO_16, do_vbitrev) +TRANS(vbitrev_w, LSX, gvec_vvv, MO_32, do_vbitrev) +TRANS(vbitrev_d, LSX, gvec_vvv, MO_64, do_vbitrev) static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, int64_t imm, uint32_t oprsz, uint32_t maxsz) @@ -3574,112 +3595,112 @@ static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs, tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]); } -TRANS(vbitrevi_b, gvec_vv_i, MO_8, do_vbitrevi) -TRANS(vbitrevi_h, gvec_vv_i, MO_16, do_vbitrevi) -TRANS(vbitrevi_w, gvec_vv_i, MO_32, do_vbitrevi) -TRANS(vbitrevi_d, gvec_vv_i, MO_64, do_vbitrevi) - -TRANS(vfrstp_b, gen_vvv, gen_helper_vfrstp_b) -TRANS(vfrstp_h, gen_vvv, gen_helper_vfrstp_h) -TRANS(vfrstpi_b, gen_vv_i, gen_helper_vfrstpi_b) -TRANS(vfrstpi_h, gen_vv_i, gen_helper_vfrstpi_h) - -TRANS(vfadd_s, gen_vvv, gen_helper_vfadd_s) -TRANS(vfadd_d, gen_vvv, gen_helper_vfadd_d) -TRANS(vfsub_s, gen_vvv, gen_helper_vfsub_s) -TRANS(vfsub_d, gen_vvv, gen_helper_vfsub_d) -TRANS(vfmul_s, gen_vvv, gen_helper_vfmul_s) -TRANS(vfmul_d, gen_vvv, gen_helper_vfmul_d) -TRANS(vfdiv_s, gen_vvv, gen_helper_vfdiv_s) -TRANS(vfdiv_d, gen_vvv, gen_helper_vfdiv_d) - -TRANS(vfmadd_s, gen_vvvv, gen_helper_vfmadd_s) -TRANS(vfmadd_d, gen_vvvv, gen_helper_vfmadd_d) -TRANS(vfmsub_s, gen_vvvv, gen_helper_vfmsub_s) -TRANS(vfmsub_d, gen_vvvv, gen_helper_vfmsub_d) -TRANS(vfnmadd_s, gen_vvvv, gen_helper_vfnmadd_s) -TRANS(vfnmadd_d, gen_vvvv, gen_helper_vfnmadd_d) -TRANS(vfnmsub_s, gen_vvvv, gen_helper_vfnmsub_s) -TRANS(vfnmsub_d, gen_vvvv, gen_helper_vfnmsub_d) - -TRANS(vfmax_s, gen_vvv, gen_helper_vfmax_s) -TRANS(vfmax_d, gen_vvv, gen_helper_vfmax_d) -TRANS(vfmin_s, gen_vvv, gen_helper_vfmin_s) -TRANS(vfmin_d, gen_vvv, gen_helper_vfmin_d) - -TRANS(vfmaxa_s, gen_vvv, gen_helper_vfmaxa_s) -TRANS(vfmaxa_d, gen_vvv, gen_helper_vfmaxa_d) -TRANS(vfmina_s, gen_vvv, gen_helper_vfmina_s) -TRANS(vfmina_d, gen_vvv, gen_helper_vfmina_d) - -TRANS(vflogb_s, gen_vv, gen_helper_vflogb_s) -TRANS(vflogb_d, gen_vv, gen_helper_vflogb_d) - -TRANS(vfclass_s, gen_vv, gen_helper_vfclass_s) -TRANS(vfclass_d, gen_vv, gen_helper_vfclass_d) - -TRANS(vfsqrt_s, gen_vv, gen_helper_vfsqrt_s) -TRANS(vfsqrt_d, gen_vv, gen_helper_vfsqrt_d) -TRANS(vfrecip_s, gen_vv, gen_helper_vfrecip_s) -TRANS(vfrecip_d, gen_vv, gen_helper_vfrecip_d) -TRANS(vfrsqrt_s, gen_vv, gen_helper_vfrsqrt_s) -TRANS(vfrsqrt_d, gen_vv, gen_helper_vfrsqrt_d) - -TRANS(vfcvtl_s_h, gen_vv, gen_helper_vfcvtl_s_h) -TRANS(vfcvth_s_h, gen_vv, gen_helper_vfcvth_s_h) -TRANS(vfcvtl_d_s, gen_vv, gen_helper_vfcvtl_d_s) -TRANS(vfcvth_d_s, gen_vv, gen_helper_vfcvth_d_s) -TRANS(vfcvt_h_s, gen_vvv, gen_helper_vfcvt_h_s) -TRANS(vfcvt_s_d, gen_vvv, gen_helper_vfcvt_s_d) - -TRANS(vfrintrne_s, gen_vv, gen_helper_vfrintrne_s) -TRANS(vfrintrne_d, gen_vv, gen_helper_vfrintrne_d) -TRANS(vfrintrz_s, gen_vv, gen_helper_vfrintrz_s) -TRANS(vfrintrz_d, gen_vv, gen_helper_vfrintrz_d) -TRANS(vfrintrp_s, gen_vv, gen_helper_vfrintrp_s) -TRANS(vfrintrp_d, gen_vv, gen_helper_vfrintrp_d) -TRANS(vfrintrm_s, gen_vv, gen_helper_vfrintrm_s) -TRANS(vfrintrm_d, gen_vv, gen_helper_vfrintrm_d) -TRANS(vfrint_s, gen_vv, gen_helper_vfrint_s) -TRANS(vfrint_d, gen_vv, gen_helper_vfrint_d) - -TRANS(vftintrne_w_s, gen_vv, gen_helper_vftintrne_w_s) -TRANS(vftintrne_l_d, gen_vv, gen_helper_vftintrne_l_d) -TRANS(vftintrz_w_s, gen_vv, gen_helper_vftintrz_w_s) -TRANS(vftintrz_l_d, gen_vv, gen_helper_vftintrz_l_d) -TRANS(vftintrp_w_s, gen_vv, gen_helper_vftintrp_w_s) -TRANS(vftintrp_l_d, gen_vv, gen_helper_vftintrp_l_d) -TRANS(vftintrm_w_s, gen_vv, gen_helper_vftintrm_w_s) -TRANS(vftintrm_l_d, gen_vv, gen_helper_vftintrm_l_d) -TRANS(vftint_w_s, gen_vv, gen_helper_vftint_w_s) -TRANS(vftint_l_d, gen_vv, gen_helper_vftint_l_d) -TRANS(vftintrz_wu_s, gen_vv, gen_helper_vftintrz_wu_s) -TRANS(vftintrz_lu_d, gen_vv, gen_helper_vftintrz_lu_d) -TRANS(vftint_wu_s, gen_vv, gen_helper_vftint_wu_s) -TRANS(vftint_lu_d, gen_vv, gen_helper_vftint_lu_d) -TRANS(vftintrne_w_d, gen_vvv, gen_helper_vftintrne_w_d) -TRANS(vftintrz_w_d, gen_vvv, gen_helper_vftintrz_w_d) -TRANS(vftintrp_w_d, gen_vvv, gen_helper_vftintrp_w_d) -TRANS(vftintrm_w_d, gen_vvv, gen_helper_vftintrm_w_d) -TRANS(vftint_w_d, gen_vvv, gen_helper_vftint_w_d) -TRANS(vftintrnel_l_s, gen_vv, gen_helper_vftintrnel_l_s) -TRANS(vftintrneh_l_s, gen_vv, gen_helper_vftintrneh_l_s) -TRANS(vftintrzl_l_s, gen_vv, gen_helper_vftintrzl_l_s) -TRANS(vftintrzh_l_s, gen_vv, gen_helper_vftintrzh_l_s) -TRANS(vftintrpl_l_s, gen_vv, gen_helper_vftintrpl_l_s) -TRANS(vftintrph_l_s, gen_vv, gen_helper_vftintrph_l_s) -TRANS(vftintrml_l_s, gen_vv, gen_helper_vftintrml_l_s) -TRANS(vftintrmh_l_s, gen_vv, gen_helper_vftintrmh_l_s) -TRANS(vftintl_l_s, gen_vv, gen_helper_vftintl_l_s) -TRANS(vftinth_l_s, gen_vv, gen_helper_vftinth_l_s) - -TRANS(vffint_s_w, gen_vv, gen_helper_vffint_s_w) -TRANS(vffint_d_l, gen_vv, gen_helper_vffint_d_l) -TRANS(vffint_s_wu, gen_vv, gen_helper_vffint_s_wu) -TRANS(vffint_d_lu, gen_vv, gen_helper_vffint_d_lu) -TRANS(vffintl_d_w, gen_vv, gen_helper_vffintl_d_w) -TRANS(vffinth_d_w, gen_vv, gen_helper_vffinth_d_w) -TRANS(vffint_s_l, gen_vvv, gen_helper_vffint_s_l) +TRANS(vbitrevi_b, LSX, gvec_vv_i, MO_8, do_vbitrevi) +TRANS(vbitrevi_h, LSX, gvec_vv_i, MO_16, do_vbitrevi) +TRANS(vbitrevi_w, LSX, gvec_vv_i, MO_32, do_vbitrevi) +TRANS(vbitrevi_d, LSX, gvec_vv_i, MO_64, do_vbitrevi) + +TRANS(vfrstp_b, LSX, gen_vvv, gen_helper_vfrstp_b) +TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h) +TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b) +TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h) + +TRANS(vfadd_s, LSX, gen_vvv, gen_helper_vfadd_s) +TRANS(vfadd_d, LSX, gen_vvv, gen_helper_vfadd_d) +TRANS(vfsub_s, LSX, gen_vvv, gen_helper_vfsub_s) +TRANS(vfsub_d, LSX, gen_vvv, gen_helper_vfsub_d) +TRANS(vfmul_s, LSX, gen_vvv, gen_helper_vfmul_s) +TRANS(vfmul_d, LSX, gen_vvv, gen_helper_vfmul_d) +TRANS(vfdiv_s, LSX, gen_vvv, gen_helper_vfdiv_s) +TRANS(vfdiv_d, LSX, gen_vvv, gen_helper_vfdiv_d) + +TRANS(vfmadd_s, LSX, gen_vvvv, gen_helper_vfmadd_s) +TRANS(vfmadd_d, LSX, gen_vvvv, gen_helper_vfmadd_d) +TRANS(vfmsub_s, LSX, gen_vvvv, gen_helper_vfmsub_s) +TRANS(vfmsub_d, LSX, gen_vvvv, gen_helper_vfmsub_d) +TRANS(vfnmadd_s, LSX, gen_vvvv, gen_helper_vfnmadd_s) +TRANS(vfnmadd_d, LSX, gen_vvvv, gen_helper_vfnmadd_d) +TRANS(vfnmsub_s, LSX, gen_vvvv, gen_helper_vfnmsub_s) +TRANS(vfnmsub_d, LSX, gen_vvvv, gen_helper_vfnmsub_d) + +TRANS(vfmax_s, LSX, gen_vvv, gen_helper_vfmax_s) +TRANS(vfmax_d, LSX, gen_vvv, gen_helper_vfmax_d) +TRANS(vfmin_s, LSX, gen_vvv, gen_helper_vfmin_s) +TRANS(vfmin_d, LSX, gen_vvv, gen_helper_vfmin_d) + +TRANS(vfmaxa_s, LSX, gen_vvv, gen_helper_vfmaxa_s) +TRANS(vfmaxa_d, LSX, gen_vvv, gen_helper_vfmaxa_d) +TRANS(vfmina_s, LSX, gen_vvv, gen_helper_vfmina_s) +TRANS(vfmina_d, LSX, gen_vvv, gen_helper_vfmina_d) + +TRANS(vflogb_s, LSX, gen_vv, gen_helper_vflogb_s) +TRANS(vflogb_d, LSX, gen_vv, gen_helper_vflogb_d) + +TRANS(vfclass_s, LSX, gen_vv, gen_helper_vfclass_s) +TRANS(vfclass_d, LSX, gen_vv, gen_helper_vfclass_d) + +TRANS(vfsqrt_s, LSX, gen_vv, gen_helper_vfsqrt_s) +TRANS(vfsqrt_d, LSX, gen_vv, gen_helper_vfsqrt_d) +TRANS(vfrecip_s, LSX, gen_vv, gen_helper_vfrecip_s) +TRANS(vfrecip_d, LSX, gen_vv, gen_helper_vfrecip_d) +TRANS(vfrsqrt_s, LSX, gen_vv, gen_helper_vfrsqrt_s) +TRANS(vfrsqrt_d, LSX, gen_vv, gen_helper_vfrsqrt_d) + +TRANS(vfcvtl_s_h, LSX, gen_vv, gen_helper_vfcvtl_s_h) +TRANS(vfcvth_s_h, LSX, gen_vv, gen_helper_vfcvth_s_h) +TRANS(vfcvtl_d_s, LSX, gen_vv, gen_helper_vfcvtl_d_s) +TRANS(vfcvth_d_s, LSX, gen_vv, gen_helper_vfcvth_d_s) +TRANS(vfcvt_h_s, LSX, gen_vvv, gen_helper_vfcvt_h_s) +TRANS(vfcvt_s_d, LSX, gen_vvv, gen_helper_vfcvt_s_d) + +TRANS(vfrintrne_s, LSX, gen_vv, gen_helper_vfrintrne_s) +TRANS(vfrintrne_d, LSX, gen_vv, gen_helper_vfrintrne_d) +TRANS(vfrintrz_s, LSX, gen_vv, gen_helper_vfrintrz_s) +TRANS(vfrintrz_d, LSX, gen_vv, gen_helper_vfrintrz_d) +TRANS(vfrintrp_s, LSX, gen_vv, gen_helper_vfrintrp_s) +TRANS(vfrintrp_d, LSX, gen_vv, gen_helper_vfrintrp_d) +TRANS(vfrintrm_s, LSX, gen_vv, gen_helper_vfrintrm_s) +TRANS(vfrintrm_d, LSX, gen_vv, gen_helper_vfrintrm_d) +TRANS(vfrint_s, LSX, gen_vv, gen_helper_vfrint_s) +TRANS(vfrint_d, LSX, gen_vv, gen_helper_vfrint_d) + +TRANS(vftintrne_w_s, LSX, gen_vv, gen_helper_vftintrne_w_s) +TRANS(vftintrne_l_d, LSX, gen_vv, gen_helper_vftintrne_l_d) +TRANS(vftintrz_w_s, LSX, gen_vv, gen_helper_vftintrz_w_s) +TRANS(vftintrz_l_d, LSX, gen_vv, gen_helper_vftintrz_l_d) +TRANS(vftintrp_w_s, LSX, gen_vv, gen_helper_vftintrp_w_s) +TRANS(vftintrp_l_d, LSX, gen_vv, gen_helper_vftintrp_l_d) +TRANS(vftintrm_w_s, LSX, gen_vv, gen_helper_vftintrm_w_s) +TRANS(vftintrm_l_d, LSX, gen_vv, gen_helper_vftintrm_l_d) +TRANS(vftint_w_s, LSX, gen_vv, gen_helper_vftint_w_s) +TRANS(vftint_l_d, LSX, gen_vv, gen_helper_vftint_l_d) +TRANS(vftintrz_wu_s, LSX, gen_vv, gen_helper_vftintrz_wu_s) +TRANS(vftintrz_lu_d, LSX, gen_vv, gen_helper_vftintrz_lu_d) +TRANS(vftint_wu_s, LSX, gen_vv, gen_helper_vftint_wu_s) +TRANS(vftint_lu_d, LSX, gen_vv, gen_helper_vftint_lu_d) +TRANS(vftintrne_w_d, LSX, gen_vvv, gen_helper_vftintrne_w_d) +TRANS(vftintrz_w_d, LSX, gen_vvv, gen_helper_vftintrz_w_d) +TRANS(vftintrp_w_d, LSX, gen_vvv, gen_helper_vftintrp_w_d) +TRANS(vftintrm_w_d, LSX, gen_vvv, gen_helper_vftintrm_w_d) +TRANS(vftint_w_d, LSX, gen_vvv, gen_helper_vftint_w_d) +TRANS(vftintrnel_l_s, LSX, gen_vv, gen_helper_vftintrnel_l_s) +TRANS(vftintrneh_l_s, LSX, gen_vv, gen_helper_vftintrneh_l_s) +TRANS(vftintrzl_l_s, LSX, gen_vv, gen_helper_vftintrzl_l_s) +TRANS(vftintrzh_l_s, LSX, gen_vv, gen_helper_vftintrzh_l_s) +TRANS(vftintrpl_l_s, LSX, gen_vv, gen_helper_vftintrpl_l_s) +TRANS(vftintrph_l_s, LSX, gen_vv, gen_helper_vftintrph_l_s) +TRANS(vftintrml_l_s, LSX, gen_vv, gen_helper_vftintrml_l_s) +TRANS(vftintrmh_l_s, LSX, gen_vv, gen_helper_vftintrmh_l_s) +TRANS(vftintl_l_s, LSX, gen_vv, gen_helper_vftintl_l_s) +TRANS(vftinth_l_s, LSX, gen_vv, gen_helper_vftinth_l_s) + +TRANS(vffint_s_w, LSX, gen_vv, gen_helper_vffint_s_w) +TRANS(vffint_d_l, LSX, gen_vv, gen_helper_vffint_d_l) +TRANS(vffint_s_wu, LSX, gen_vv, gen_helper_vffint_s_wu) +TRANS(vffint_d_lu, LSX, gen_vv, gen_helper_vffint_d_lu) +TRANS(vffintl_d_w, LSX, gen_vv, gen_helper_vffintl_d_w) +TRANS(vffinth_d_w, LSX, gen_vv, gen_helper_vffinth_d_w) +TRANS(vffint_s_l, LSX, gen_vvv, gen_helper_vffint_s_l) static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond) { @@ -3823,48 +3844,48 @@ static bool do_## NAME ##_u(DisasContext *ctx, arg_vv_i *a, MemOp mop) \ DO_CMPI_U(vslei) DO_CMPI_U(vslti) -TRANS(vseq_b, do_cmp, MO_8, TCG_COND_EQ) -TRANS(vseq_h, do_cmp, MO_16, TCG_COND_EQ) -TRANS(vseq_w, do_cmp, MO_32, TCG_COND_EQ) -TRANS(vseq_d, do_cmp, MO_64, TCG_COND_EQ) -TRANS(vseqi_b, do_vseqi_s, MO_8) -TRANS(vseqi_h, do_vseqi_s, MO_16) -TRANS(vseqi_w, do_vseqi_s, MO_32) -TRANS(vseqi_d, do_vseqi_s, MO_64) - -TRANS(vsle_b, do_cmp, MO_8, TCG_COND_LE) -TRANS(vsle_h, do_cmp, MO_16, TCG_COND_LE) -TRANS(vsle_w, do_cmp, MO_32, TCG_COND_LE) -TRANS(vsle_d, do_cmp, MO_64, TCG_COND_LE) -TRANS(vslei_b, do_vslei_s, MO_8) -TRANS(vslei_h, do_vslei_s, MO_16) -TRANS(vslei_w, do_vslei_s, MO_32) -TRANS(vslei_d, do_vslei_s, MO_64) -TRANS(vsle_bu, do_cmp, MO_8, TCG_COND_LEU) -TRANS(vsle_hu, do_cmp, MO_16, TCG_COND_LEU) -TRANS(vsle_wu, do_cmp, MO_32, TCG_COND_LEU) -TRANS(vsle_du, do_cmp, MO_64, TCG_COND_LEU) -TRANS(vslei_bu, do_vslei_u, MO_8) -TRANS(vslei_hu, do_vslei_u, MO_16) -TRANS(vslei_wu, do_vslei_u, MO_32) -TRANS(vslei_du, do_vslei_u, MO_64) - -TRANS(vslt_b, do_cmp, MO_8, TCG_COND_LT) -TRANS(vslt_h, do_cmp, MO_16, TCG_COND_LT) -TRANS(vslt_w, do_cmp, MO_32, TCG_COND_LT) -TRANS(vslt_d, do_cmp, MO_64, TCG_COND_LT) -TRANS(vslti_b, do_vslti_s, MO_8) -TRANS(vslti_h, do_vslti_s, MO_16) -TRANS(vslti_w, do_vslti_s, MO_32) -TRANS(vslti_d, do_vslti_s, MO_64) -TRANS(vslt_bu, do_cmp, MO_8, TCG_COND_LTU) -TRANS(vslt_hu, do_cmp, MO_16, TCG_COND_LTU) -TRANS(vslt_wu, do_cmp, MO_32, TCG_COND_LTU) -TRANS(vslt_du, do_cmp, MO_64, TCG_COND_LTU) -TRANS(vslti_bu, do_vslti_u, MO_8) -TRANS(vslti_hu, do_vslti_u, MO_16) -TRANS(vslti_wu, do_vslti_u, MO_32) -TRANS(vslti_du, do_vslti_u, MO_64) +TRANS(vseq_b, LSX, do_cmp, MO_8, TCG_COND_EQ) +TRANS(vseq_h, LSX, do_cmp, MO_16, TCG_COND_EQ) +TRANS(vseq_w, LSX, do_cmp, MO_32, TCG_COND_EQ) +TRANS(vseq_d, LSX, do_cmp, MO_64, TCG_COND_EQ) +TRANS(vseqi_b, LSX, do_vseqi_s, MO_8) +TRANS(vseqi_h, LSX, do_vseqi_s, MO_16) +TRANS(vseqi_w, LSX, do_vseqi_s, MO_32) +TRANS(vseqi_d, LSX, do_vseqi_s, MO_64) + +TRANS(vsle_b, LSX, do_cmp, MO_8, TCG_COND_LE) +TRANS(vsle_h, LSX, do_cmp, MO_16, TCG_COND_LE) +TRANS(vsle_w, LSX, do_cmp, MO_32, TCG_COND_LE) +TRANS(vsle_d, LSX, do_cmp, MO_64, TCG_COND_LE) +TRANS(vslei_b, LSX, do_vslei_s, MO_8) +TRANS(vslei_h, LSX, do_vslei_s, MO_16) +TRANS(vslei_w, LSX, do_vslei_s, MO_32) +TRANS(vslei_d, LSX, do_vslei_s, MO_64) +TRANS(vsle_bu, LSX, do_cmp, MO_8, TCG_COND_LEU) +TRANS(vsle_hu, LSX, do_cmp, MO_16, TCG_COND_LEU) +TRANS(vsle_wu, LSX, do_cmp, MO_32, TCG_COND_LEU) +TRANS(vsle_du, LSX, do_cmp, MO_64, TCG_COND_LEU) +TRANS(vslei_bu, LSX, do_vslei_u, MO_8) +TRANS(vslei_hu, LSX, do_vslei_u, MO_16) +TRANS(vslei_wu, LSX, do_vslei_u, MO_32) +TRANS(vslei_du, LSX, do_vslei_u, MO_64) + +TRANS(vslt_b, LSX, do_cmp, MO_8, TCG_COND_LT) +TRANS(vslt_h, LSX, do_cmp, MO_16, TCG_COND_LT) +TRANS(vslt_w, LSX, do_cmp, MO_32, TCG_COND_LT) +TRANS(vslt_d, LSX, do_cmp, MO_64, TCG_COND_LT) +TRANS(vslti_b, LSX, do_vslti_s, MO_8) +TRANS(vslti_h, LSX, do_vslti_s, MO_16) +TRANS(vslti_w, LSX, do_vslti_s, MO_32) +TRANS(vslti_d, LSX, do_vslti_s, MO_64) +TRANS(vslt_bu, LSX, do_cmp, MO_8, TCG_COND_LTU) +TRANS(vslt_hu, LSX, do_cmp, MO_16, TCG_COND_LTU) +TRANS(vslt_wu, LSX, do_cmp, MO_32, TCG_COND_LTU) +TRANS(vslt_du, LSX, do_cmp, MO_64, TCG_COND_LTU) +TRANS(vslti_bu, LSX, do_vslti_u, MO_8) +TRANS(vslti_hu, LSX, do_vslti_u, MO_16) +TRANS(vslti_wu, LSX, do_vslti_u, MO_32) +TRANS(vslti_du, LSX, do_vslti_u, MO_64) static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a) { @@ -3874,6 +3895,10 @@ static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a) TCGv_i32 vj = tcg_constant_i32(a->vj); TCGv_i32 vk = tcg_constant_i32(a->vk); + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s); @@ -3891,6 +3916,12 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a) TCGv_i32 vj = tcg_constant_i32(a->vj); TCGv_i32 vk = tcg_constant_i32(a->vk); + if (!avail_LSX(ctx)) { + return false; + } + + CHECK_SXE; + fn = (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d); flags = get_fcmp_flags(a->fcond >> 1); fn(cpu_env, vd, vj, vk, tcg_constant_i32(flags)); @@ -3900,6 +3931,10 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a) static bool trans_vbitsel_v(DisasContext *ctx, arg_vvvv *a) { + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_bitsel(MO_64, vec_full_offset(a->vd), vec_full_offset(a->va), @@ -3922,6 +3957,10 @@ static bool trans_vbitseli_b(DisasContext *ctx, arg_vv_i *a) .load_dest = true }; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_2i(vec_full_offset(a->vd), vec_full_offset(a->vj), @@ -3941,6 +3980,10 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \ get_vreg64(ah, a->vj, 1); \ get_vreg64(al, a->vj, 0); \ \ + if (!avail_LSX(ctx)) { \ + return false; \ + } \ + \ CHECK_SXE; \ tcg_gen_or_i64(t1, al, ah); \ tcg_gen_setcondi_i64(COND, t1, t1, 0); \ @@ -3952,18 +3995,23 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \ VSET(vseteqz_v, TCG_COND_EQ) VSET(vsetnez_v, TCG_COND_NE) -TRANS(vsetanyeqz_b, gen_cv, gen_helper_vsetanyeqz_b) -TRANS(vsetanyeqz_h, gen_cv, gen_helper_vsetanyeqz_h) -TRANS(vsetanyeqz_w, gen_cv, gen_helper_vsetanyeqz_w) -TRANS(vsetanyeqz_d, gen_cv, gen_helper_vsetanyeqz_d) -TRANS(vsetallnez_b, gen_cv, gen_helper_vsetallnez_b) -TRANS(vsetallnez_h, gen_cv, gen_helper_vsetallnez_h) -TRANS(vsetallnez_w, gen_cv, gen_helper_vsetallnez_w) -TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d) +TRANS(vsetanyeqz_b, LSX, gen_cv, gen_helper_vsetanyeqz_b) +TRANS(vsetanyeqz_h, LSX, gen_cv, gen_helper_vsetanyeqz_h) +TRANS(vsetanyeqz_w, LSX, gen_cv, gen_helper_vsetanyeqz_w) +TRANS(vsetanyeqz_d, LSX, gen_cv, gen_helper_vsetanyeqz_d) +TRANS(vsetallnez_b, LSX, gen_cv, gen_helper_vsetallnez_b) +TRANS(vsetallnez_h, LSX, gen_cv, gen_helper_vsetallnez_h) +TRANS(vsetallnez_w, LSX, gen_cv, gen_helper_vsetallnez_w) +TRANS(vsetallnez_d, LSX, gen_cv, gen_helper_vsetallnez_d) static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_st8_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm))); @@ -3973,6 +4021,11 @@ static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a) static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_st16_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm))); @@ -3982,6 +4035,11 @@ static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a) static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_st32_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm))); @@ -3991,6 +4049,11 @@ static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_st_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm))); @@ -4000,6 +4063,11 @@ static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld8s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); @@ -4009,6 +4077,11 @@ static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld16s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); @@ -4018,6 +4091,11 @@ static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld32s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); @@ -4027,6 +4105,11 @@ static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); @@ -4036,6 +4119,11 @@ static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld8u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); @@ -4045,6 +4133,11 @@ static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld16u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); @@ -4054,6 +4147,11 @@ static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld32u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); @@ -4063,6 +4161,11 @@ static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) { TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); @@ -4072,6 +4175,11 @@ static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) { TCGv src = gpr_src(ctx, a->rj, EXT_NONE); + + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd), @@ -4079,13 +4187,17 @@ static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) return true; } -TRANS(vreplgr2vr_b, gvec_dup, MO_8) -TRANS(vreplgr2vr_h, gvec_dup, MO_16) -TRANS(vreplgr2vr_w, gvec_dup, MO_32) -TRANS(vreplgr2vr_d, gvec_dup, MO_64) +TRANS(vreplgr2vr_b, LSX, gvec_dup, MO_8) +TRANS(vreplgr2vr_h, LSX, gvec_dup, MO_16) +TRANS(vreplgr2vr_w, LSX, gvec_dup, MO_32) +TRANS(vreplgr2vr_d, LSX, gvec_dup, MO_64) static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a) { + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_dup_mem(MO_8,vec_full_offset(a->vd), offsetof(CPULoongArchState, @@ -4096,6 +4208,10 @@ static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a) static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a) { + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_dup_mem(MO_16, vec_full_offset(a->vd), offsetof(CPULoongArchState, @@ -4105,6 +4221,10 @@ static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a) } static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a) { + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_dup_mem(MO_32, vec_full_offset(a->vd), offsetof(CPULoongArchState, @@ -4114,6 +4234,10 @@ static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a) } static bool trans_vreplvei_d(DisasContext *ctx, arg_vv_i *a) { + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_gvec_dup_mem(MO_64, vec_full_offset(a->vd), offsetof(CPULoongArchState, @@ -4129,6 +4253,10 @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit, TCGv_ptr t1 = tcg_temp_new_ptr(); TCGv_i64 t2 = tcg_temp_new_i64(); + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; tcg_gen_andi_i64(t0, gpr_src(ctx, a->rk, EXT_NONE), (LSX_LEN/bit) -1); @@ -4145,16 +4273,20 @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit, return true; } -TRANS(vreplve_b, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64) -TRANS(vreplve_h, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64) -TRANS(vreplve_w, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64) -TRANS(vreplve_d, gen_vreplve, MO_64, 64, tcg_gen_ld_i64) +TRANS(vreplve_b, LSX, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64) +TRANS(vreplve_h, LSX, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64) +TRANS(vreplve_w, LSX, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64) +TRANS(vreplve_d, LSX, gen_vreplve, MO_64, 64, tcg_gen_ld_i64) static bool trans_vbsll_v(DisasContext *ctx, arg_vv_i *a) { int ofs; TCGv_i64 desthigh, destlow, high, low; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; desthigh = tcg_temp_new_i64(); @@ -4185,6 +4317,10 @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a) TCGv_i64 desthigh, destlow, high, low; int ofs; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; desthigh = tcg_temp_new_i64(); @@ -4210,55 +4346,59 @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a) return true; } -TRANS(vpackev_b, gen_vvv, gen_helper_vpackev_b) -TRANS(vpackev_h, gen_vvv, gen_helper_vpackev_h) -TRANS(vpackev_w, gen_vvv, gen_helper_vpackev_w) -TRANS(vpackev_d, gen_vvv, gen_helper_vpackev_d) -TRANS(vpackod_b, gen_vvv, gen_helper_vpackod_b) -TRANS(vpackod_h, gen_vvv, gen_helper_vpackod_h) -TRANS(vpackod_w, gen_vvv, gen_helper_vpackod_w) -TRANS(vpackod_d, gen_vvv, gen_helper_vpackod_d) - -TRANS(vpickev_b, gen_vvv, gen_helper_vpickev_b) -TRANS(vpickev_h, gen_vvv, gen_helper_vpickev_h) -TRANS(vpickev_w, gen_vvv, gen_helper_vpickev_w) -TRANS(vpickev_d, gen_vvv, gen_helper_vpickev_d) -TRANS(vpickod_b, gen_vvv, gen_helper_vpickod_b) -TRANS(vpickod_h, gen_vvv, gen_helper_vpickod_h) -TRANS(vpickod_w, gen_vvv, gen_helper_vpickod_w) -TRANS(vpickod_d, gen_vvv, gen_helper_vpickod_d) - -TRANS(vilvl_b, gen_vvv, gen_helper_vilvl_b) -TRANS(vilvl_h, gen_vvv, gen_helper_vilvl_h) -TRANS(vilvl_w, gen_vvv, gen_helper_vilvl_w) -TRANS(vilvl_d, gen_vvv, gen_helper_vilvl_d) -TRANS(vilvh_b, gen_vvv, gen_helper_vilvh_b) -TRANS(vilvh_h, gen_vvv, gen_helper_vilvh_h) -TRANS(vilvh_w, gen_vvv, gen_helper_vilvh_w) -TRANS(vilvh_d, gen_vvv, gen_helper_vilvh_d) - -TRANS(vshuf_b, gen_vvvv, gen_helper_vshuf_b) -TRANS(vshuf_h, gen_vvv, gen_helper_vshuf_h) -TRANS(vshuf_w, gen_vvv, gen_helper_vshuf_w) -TRANS(vshuf_d, gen_vvv, gen_helper_vshuf_d) -TRANS(vshuf4i_b, gen_vv_i, gen_helper_vshuf4i_b) -TRANS(vshuf4i_h, gen_vv_i, gen_helper_vshuf4i_h) -TRANS(vshuf4i_w, gen_vv_i, gen_helper_vshuf4i_w) -TRANS(vshuf4i_d, gen_vv_i, gen_helper_vshuf4i_d) - -TRANS(vpermi_w, gen_vv_i, gen_helper_vpermi_w) - -TRANS(vextrins_b, gen_vv_i, gen_helper_vextrins_b) -TRANS(vextrins_h, gen_vv_i, gen_helper_vextrins_h) -TRANS(vextrins_w, gen_vv_i, gen_helper_vextrins_w) -TRANS(vextrins_d, gen_vv_i, gen_helper_vextrins_d) +TRANS(vpackev_b, LSX, gen_vvv, gen_helper_vpackev_b) +TRANS(vpackev_h, LSX, gen_vvv, gen_helper_vpackev_h) +TRANS(vpackev_w, LSX, gen_vvv, gen_helper_vpackev_w) +TRANS(vpackev_d, LSX, gen_vvv, gen_helper_vpackev_d) +TRANS(vpackod_b, LSX, gen_vvv, gen_helper_vpackod_b) +TRANS(vpackod_h, LSX, gen_vvv, gen_helper_vpackod_h) +TRANS(vpackod_w, LSX, gen_vvv, gen_helper_vpackod_w) +TRANS(vpackod_d, LSX, gen_vvv, gen_helper_vpackod_d) + +TRANS(vpickev_b, LSX, gen_vvv, gen_helper_vpickev_b) +TRANS(vpickev_h, LSX, gen_vvv, gen_helper_vpickev_h) +TRANS(vpickev_w, LSX, gen_vvv, gen_helper_vpickev_w) +TRANS(vpickev_d, LSX, gen_vvv, gen_helper_vpickev_d) +TRANS(vpickod_b, LSX, gen_vvv, gen_helper_vpickod_b) +TRANS(vpickod_h, LSX, gen_vvv, gen_helper_vpickod_h) +TRANS(vpickod_w, LSX, gen_vvv, gen_helper_vpickod_w) +TRANS(vpickod_d, LSX, gen_vvv, gen_helper_vpickod_d) + +TRANS(vilvl_b, LSX, gen_vvv, gen_helper_vilvl_b) +TRANS(vilvl_h, LSX, gen_vvv, gen_helper_vilvl_h) +TRANS(vilvl_w, LSX, gen_vvv, gen_helper_vilvl_w) +TRANS(vilvl_d, LSX, gen_vvv, gen_helper_vilvl_d) +TRANS(vilvh_b, LSX, gen_vvv, gen_helper_vilvh_b) +TRANS(vilvh_h, LSX, gen_vvv, gen_helper_vilvh_h) +TRANS(vilvh_w, LSX, gen_vvv, gen_helper_vilvh_w) +TRANS(vilvh_d, LSX, gen_vvv, gen_helper_vilvh_d) + +TRANS(vshuf_b, LSX, gen_vvvv, gen_helper_vshuf_b) +TRANS(vshuf_h, LSX, gen_vvv, gen_helper_vshuf_h) +TRANS(vshuf_w, LSX, gen_vvv, gen_helper_vshuf_w) +TRANS(vshuf_d, LSX, gen_vvv, gen_helper_vshuf_d) +TRANS(vshuf4i_b, LSX, gen_vv_i, gen_helper_vshuf4i_b) +TRANS(vshuf4i_h, LSX, gen_vv_i, gen_helper_vshuf4i_h) +TRANS(vshuf4i_w, LSX, gen_vv_i, gen_helper_vshuf4i_w) +TRANS(vshuf4i_d, LSX, gen_vv_i, gen_helper_vshuf4i_d) + +TRANS(vpermi_w, LSX, gen_vv_i, gen_helper_vpermi_w) + +TRANS(vextrins_b, LSX, gen_vv_i, gen_helper_vextrins_b) +TRANS(vextrins_h, LSX, gen_vv_i, gen_helper_vextrins_h) +TRANS(vextrins_w, LSX, gen_vv_i, gen_helper_vextrins_w) +TRANS(vextrins_d, LSX, gen_vv_i, gen_helper_vextrins_d) static bool trans_vld(DisasContext *ctx, arg_vr_i *a) { - TCGv addr, temp; + TCGv addr; TCGv_i64 rl, rh; TCGv_i128 val; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; addr = gpr_src(ctx, a->rj, EXT_NONE); @@ -4266,11 +4406,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) rl = tcg_temp_new_i64(); rh = tcg_temp_new_i64(); - if (a->imm) { - temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); tcg_gen_extr_i128_i64(rl, rh, val); @@ -4282,10 +4418,14 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a) static bool trans_vst(DisasContext *ctx, arg_vr_i *a) { - TCGv addr, temp; + TCGv addr; TCGv_i128 val; TCGv_i64 ah, al; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; addr = gpr_src(ctx, a->rj, EXT_NONE); @@ -4293,11 +4433,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a) ah = tcg_temp_new_i64(); al = tcg_temp_new_i64(); - if (a->imm) { - temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); @@ -4313,16 +4449,19 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a) TCGv_i64 rl, rh; TCGv_i128 val; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; - addr = tcg_temp_new(); src1 = gpr_src(ctx, a->rj, EXT_NONE); src2 = gpr_src(ctx, a->rk, EXT_NONE); val = tcg_temp_new_i128(); rl = tcg_temp_new_i64(); rh = tcg_temp_new_i64(); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE); tcg_gen_extr_i128_i64(rl, rh, val); set_vreg64(rh, a->vd, 1); @@ -4337,16 +4476,19 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) TCGv_i64 ah, al; TCGv_i128 val; + if (!avail_LSX(ctx)) { + return false; + } + CHECK_SXE; - addr = tcg_temp_new(); src1 = gpr_src(ctx, a->rj, EXT_NONE); src2 = gpr_src(ctx, a->rk, EXT_NONE); val = tcg_temp_new_i128(); ah = tcg_temp_new_i64(); al = tcg_temp_new_i64(); - tcg_gen_add_tl(addr, src1, src2); + addr = make_address_x(ctx, src1, src2); get_vreg64(ah, a->vd, 1); get_vreg64(al, a->vd, 0); tcg_gen_concat_i64_i128(val, al, ah); @@ -4358,19 +4500,19 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a) #define VLDREPL(NAME, MO) \ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \ { \ - TCGv addr, temp; \ + TCGv addr; \ TCGv_i64 val; \ \ + if (!avail_LSX(ctx)) { \ + return false; \ + } \ + \ CHECK_SXE; \ \ addr = gpr_src(ctx, a->rj, EXT_NONE); \ val = tcg_temp_new_i64(); \ \ - if (a->imm) { \ - temp = tcg_temp_new(); \ - tcg_gen_addi_tl(temp, addr, a->imm); \ - addr = temp; \ - } \ + addr = make_address_i(ctx, addr, a->imm); \ \ tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, MO); \ tcg_gen_gvec_dup_i64(MO, vec_full_offset(a->vd), 16, ctx->vl/8, val); \ @@ -4386,19 +4528,19 @@ VLDREPL(vldrepl_d, MO_64) #define VSTELM(NAME, MO, E) \ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \ { \ - TCGv addr, temp; \ + TCGv addr; \ TCGv_i64 val; \ \ + if (!avail_LSX(ctx)) { \ + return false; \ + } \ + \ CHECK_SXE; \ \ addr = gpr_src(ctx, a->rj, EXT_NONE); \ val = tcg_temp_new_i64(); \ \ - if (a->imm) { \ - temp = tcg_temp_new(); \ - tcg_gen_addi_tl(temp, addr, a->imm); \ - addr = temp; \ - } \ + addr = make_address_i(ctx, addr, a->imm); \ \ tcg_gen_ld_i64(val, cpu_env, \ offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))); \ diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc index 75cfdf59ad..d9d062235a 100644 --- a/target/loongarch/insn_trans/trans_memory.c.inc +++ b/target/loongarch/insn_trans/trans_memory.c.inc @@ -8,11 +8,7 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - if (a->imm) { - TCGv temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -24,11 +20,7 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv data = gpr_src(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - if (a->imm) { - TCGv temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); return true; @@ -39,9 +31,8 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr = tcg_temp_new(); + TCGv addr = make_address_x(ctx, src1, src2); - tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -53,9 +44,8 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop) TCGv data = gpr_src(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); - TCGv addr = tcg_temp_new(); + TCGv addr = make_address_x(ctx, src1, src2); - tcg_gen_add_tl(addr, src1, src2); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); return true; @@ -68,6 +58,7 @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop) TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); gen_helper_asrtgt_d(cpu_env, src1, src2); + src1 = make_address_i(ctx, src1, 0); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -81,6 +72,7 @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop) TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); gen_helper_asrtle_d(cpu_env, src1, src2); + src1 = make_address_i(ctx, src1, 0); tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -94,6 +86,7 @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop) TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); gen_helper_asrtgt_d(cpu_env, src1, src2); + src1 = make_address_i(ctx, src1, 0); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); return true; @@ -106,6 +99,7 @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop) TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE); gen_helper_asrtle_d(cpu_env, src1, src2); + src1 = make_address_i(ctx, src1, 0); tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop); return true; @@ -133,11 +127,7 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - if (a->imm) { - TCGv temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop); gen_set_gpr(a->rd, dest, EXT_NONE); @@ -149,55 +139,51 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop) TCGv data = gpr_src(ctx, a->rd, EXT_NONE); TCGv addr = gpr_src(ctx, a->rj, EXT_NONE); - if (a->imm) { - TCGv temp = tcg_temp_new(); - tcg_gen_addi_tl(temp, addr, a->imm); - addr = temp; - } + addr = make_address_i(ctx, addr, a->imm); tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop); return true; } -TRANS(ld_b, gen_load, MO_SB) -TRANS(ld_h, gen_load, MO_TESW) -TRANS(ld_w, gen_load, MO_TESL) -TRANS(ld_d, gen_load, MO_TEUQ) -TRANS(st_b, gen_store, MO_UB) -TRANS(st_h, gen_store, MO_TEUW) -TRANS(st_w, gen_store, MO_TEUL) -TRANS(st_d, gen_store, MO_TEUQ) -TRANS(ld_bu, gen_load, MO_UB) -TRANS(ld_hu, gen_load, MO_TEUW) -TRANS(ld_wu, gen_load, MO_TEUL) -TRANS(ldx_b, gen_loadx, MO_SB) -TRANS(ldx_h, gen_loadx, MO_TESW) -TRANS(ldx_w, gen_loadx, MO_TESL) -TRANS(ldx_d, gen_loadx, MO_TEUQ) -TRANS(stx_b, gen_storex, MO_UB) -TRANS(stx_h, gen_storex, MO_TEUW) -TRANS(stx_w, gen_storex, MO_TEUL) -TRANS(stx_d, gen_storex, MO_TEUQ) -TRANS(ldx_bu, gen_loadx, MO_UB) -TRANS(ldx_hu, gen_loadx, MO_TEUW) -TRANS(ldx_wu, gen_loadx, MO_TEUL) -TRANS(ldptr_w, gen_ldptr, MO_TESL) -TRANS(stptr_w, gen_stptr, MO_TEUL) -TRANS(ldptr_d, gen_ldptr, MO_TEUQ) -TRANS(stptr_d, gen_stptr, MO_TEUQ) -TRANS(ldgt_b, gen_load_gt, MO_SB) -TRANS(ldgt_h, gen_load_gt, MO_TESW) -TRANS(ldgt_w, gen_load_gt, MO_TESL) -TRANS(ldgt_d, gen_load_gt, MO_TEUQ) -TRANS(ldle_b, gen_load_le, MO_SB) -TRANS(ldle_h, gen_load_le, MO_TESW) -TRANS(ldle_w, gen_load_le, MO_TESL) -TRANS(ldle_d, gen_load_le, MO_TEUQ) -TRANS(stgt_b, gen_store_gt, MO_UB) -TRANS(stgt_h, gen_store_gt, MO_TEUW) -TRANS(stgt_w, gen_store_gt, MO_TEUL) -TRANS(stgt_d, gen_store_gt, MO_TEUQ) -TRANS(stle_b, gen_store_le, MO_UB) -TRANS(stle_h, gen_store_le, MO_TEUW) -TRANS(stle_w, gen_store_le, MO_TEUL) -TRANS(stle_d, gen_store_le, MO_TEUQ) +TRANS(ld_b, ALL, gen_load, MO_SB) +TRANS(ld_h, ALL, gen_load, MO_TESW) +TRANS(ld_w, ALL, gen_load, MO_TESL) +TRANS(ld_d, 64, gen_load, MO_TEUQ) +TRANS(st_b, ALL, gen_store, MO_UB) +TRANS(st_h, ALL, gen_store, MO_TEUW) +TRANS(st_w, ALL, gen_store, MO_TEUL) +TRANS(st_d, 64, gen_store, MO_TEUQ) +TRANS(ld_bu, ALL, gen_load, MO_UB) +TRANS(ld_hu, ALL, gen_load, MO_TEUW) +TRANS(ld_wu, 64, gen_load, MO_TEUL) +TRANS(ldx_b, 64, gen_loadx, MO_SB) +TRANS(ldx_h, 64, gen_loadx, MO_TESW) +TRANS(ldx_w, 64, gen_loadx, MO_TESL) +TRANS(ldx_d, 64, gen_loadx, MO_TEUQ) +TRANS(stx_b, 64, gen_storex, MO_UB) +TRANS(stx_h, 64, gen_storex, MO_TEUW) +TRANS(stx_w, 64, gen_storex, MO_TEUL) +TRANS(stx_d, 64, gen_storex, MO_TEUQ) +TRANS(ldx_bu, 64, gen_loadx, MO_UB) +TRANS(ldx_hu, 64, gen_loadx, MO_TEUW) +TRANS(ldx_wu, 64, gen_loadx, MO_TEUL) +TRANS(ldptr_w, 64, gen_ldptr, MO_TESL) +TRANS(stptr_w, 64, gen_stptr, MO_TEUL) +TRANS(ldptr_d, 64, gen_ldptr, MO_TEUQ) +TRANS(stptr_d, 64, gen_stptr, MO_TEUQ) +TRANS(ldgt_b, 64, gen_load_gt, MO_SB) +TRANS(ldgt_h, 64, gen_load_gt, MO_TESW) +TRANS(ldgt_w, 64, gen_load_gt, MO_TESL) +TRANS(ldgt_d, 64, gen_load_gt, MO_TEUQ) +TRANS(ldle_b, 64, gen_load_le, MO_SB) +TRANS(ldle_h, 64, gen_load_le, MO_TESW) +TRANS(ldle_w, 64, gen_load_le, MO_TESL) +TRANS(ldle_d, 64, gen_load_le, MO_TEUQ) +TRANS(stgt_b, 64, gen_store_gt, MO_UB) +TRANS(stgt_h, 64, gen_store_gt, MO_TEUW) +TRANS(stgt_w, 64, gen_store_gt, MO_TEUL) +TRANS(stgt_d, 64, gen_store_gt, MO_TEUQ) +TRANS(stle_b, 64, gen_store_le, MO_UB) +TRANS(stle_h, 64, gen_store_le, MO_TEUW) +TRANS(stle_w, 64, gen_store_le, MO_TEUL) +TRANS(stle_d, 64, gen_store_le, MO_TEUQ) diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 9c9de090f0..4cb701b4b5 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -312,14 +312,14 @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a, return true; } -TRANS(iocsrrd_b, gen_iocsrrd, gen_helper_iocsrrd_b) -TRANS(iocsrrd_h, gen_iocsrrd, gen_helper_iocsrrd_h) -TRANS(iocsrrd_w, gen_iocsrrd, gen_helper_iocsrrd_w) -TRANS(iocsrrd_d, gen_iocsrrd, gen_helper_iocsrrd_d) -TRANS(iocsrwr_b, gen_iocsrwr, gen_helper_iocsrwr_b) -TRANS(iocsrwr_h, gen_iocsrwr, gen_helper_iocsrwr_h) -TRANS(iocsrwr_w, gen_iocsrwr, gen_helper_iocsrwr_w) -TRANS(iocsrwr_d, gen_iocsrwr, gen_helper_iocsrwr_d) +TRANS(iocsrrd_b, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_b) +TRANS(iocsrrd_h, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_h) +TRANS(iocsrrd_w, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_w) +TRANS(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d) +TRANS(iocsrwr_b, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_b) +TRANS(iocsrwr_h, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_h) +TRANS(iocsrwr_w, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_w) +TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d) static void check_mmu_idx(DisasContext *ctx) { @@ -437,6 +437,10 @@ static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a) TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx); TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE); + if (!avail_LSPW(ctx)) { + return true; + } + if (check_plv(ctx)) { return false; } @@ -450,6 +454,10 @@ static bool trans_lddir(DisasContext *ctx, arg_lddir *a) TCGv src = gpr_src(ctx, a->rj, EXT_NONE); TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); + if (!avail_LSPW(ctx)) { + return true; + } + if (check_plv(ctx)) { return false; } diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc index bf5428a2ba..2f4bd6ff28 100644 --- a/target/loongarch/insn_trans/trans_shift.c.inc +++ b/target/loongarch/insn_trans/trans_shift.c.inc @@ -72,24 +72,28 @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a) TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE); TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO); + if (!avail_64(ctx)) { + return false; + } + tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm); gen_set_gpr(a->rd, dest, EXT_NONE); return true; } -TRANS(sll_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w) -TRANS(srl_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w) -TRANS(sra_w, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w) -TRANS(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d) -TRANS(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d) -TRANS(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d) -TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) -TRANS(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d) -TRANS(slli_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl) -TRANS(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl) -TRANS(srli_w, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl) -TRANS(srli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl) -TRANS(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl) -TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) -TRANS(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl) +TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w) +TRANS(srl_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w) +TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w) +TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d) +TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d) +TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d) +TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) +TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d) +TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl) +TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl) +TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl) +TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl) +TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl) +TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) +TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl) diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index 60335a05e2..cf84f20aba 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -114,14 +114,14 @@ void helper_ertn(CPULoongArchState *env) env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0); env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 0); env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 1); - env->pc = env->CSR_TLBRERA; + set_pc(env, env->CSR_TLBRERA); qemu_log_mask(CPU_LOG_INT, "%s: TLBRERA " TARGET_FMT_lx "\n", __func__, env->CSR_TLBRERA); } else { csr_pplv = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PPLV); csr_pie = FIELD_EX64(env->CSR_PRMD, CSR_PRMD, PIE); - env->pc = env->CSR_ERA; + set_pc(env, env->CSR_ERA); qemu_log_mask(CPU_LOG_INT, "%s: ERA " TARGET_FMT_lx "\n", __func__, env->CSR_ERA); } diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index 6e00190547..c8b8b0497f 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical, tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V); tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D); tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV); - tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN); - tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX); - tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR); - tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV); + if (is_la64(env)) { + tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); + tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX); + tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR); + tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV); + } else { + tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN); + tlb_nx = 0; + tlb_nr = 0; + tlb_rplv = 0; + } /* Check access rights */ if (!tlb_v) { @@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical, * tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15] * need adjust. */ - *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) | + *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) | (address & MAKE_64BIT_MASK(0, tlb_ps)); *prot = PAGE_READ; if (tlb_d) { @@ -166,6 +173,18 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, return TLBRET_NOMATCH; } +static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va, + target_ulong dmw) +{ + if (is_la64(env)) { + return va & TARGET_VIRT_MASK; + } else { + uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG); + return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \ + (pseg << R_CSR_DMW_32_VSEG_SHIFT); + } +} + static int get_physical_address(CPULoongArchState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type, int mmu_idx) @@ -185,12 +204,20 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical, } plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT); - base_v = address >> R_CSR_DMW_VSEG_SHIFT; + if (is_la64(env)) { + base_v = address >> R_CSR_DMW_64_VSEG_SHIFT; + } else { + base_v = address >> R_CSR_DMW_32_VSEG_SHIFT; + } /* Check direct map window */ for (int i = 0; i < 4; i++) { - base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG); + if (is_la64(env)) { + base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG); + } else { + base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG); + } if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) { - *physical = dmw_va2pa(address); + *physical = dmw_va2pa(env, address, env->CSR_DMW[i]); *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; return TLBRET_MATCH; } @@ -273,8 +300,13 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address, if (tlb_error == TLBRET_NOMATCH) { env->CSR_TLBRBADV = address; - env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN, - extract64(address, 13, 35)); + if (is_la64(env)) { + env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64, + VPPN, extract64(address, 13, 35)); + } else { + env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32, + VPPN, extract64(address, 13, 19)); + } } else { if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) { env->CSR_BADV = address; @@ -339,12 +371,20 @@ static void fill_tlb_entry(CPULoongArchState *env, int index) if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); - csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN); + if (is_la64(env)) { + csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN); + } else { + csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN); + } lo0 = env->CSR_TLBRELO0; lo1 = env->CSR_TLBRELO1; } else { csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); - csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN); + if (is_la64(env)) { + csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); + } else { + csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); + } lo0 = env->CSR_TLBELO0; lo1 = env->CSR_TLBELO1; } @@ -464,7 +504,7 @@ void helper_tlbfill(CPULoongArchState *env) if (pagesize == stlb_ps) { /* Only write into STLB bits [47:13] */ - address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT); + address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); /* Choose one set ramdomly */ set = get_random_tlb(0, 7); diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 3146a2d4ac..fd393ed76d 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -86,6 +86,10 @@ void generate_exception(DisasContext *ctx, int excp) static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) { + if (ctx->va32) { + dest = (uint32_t) dest; + } + if (translator_use_goto_tb(&ctx->base, dest)) { tcg_gen_goto_tb(n); tcg_gen_movi_tl(cpu_pc, dest); @@ -119,7 +123,13 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase, ctx->vl = LSX_LEN; } + ctx->la64 = is_la64(env); + ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0; + ctx->zero = tcg_constant_tl(0); + + ctx->cpucfg1 = env->cpucfg[1]; + ctx->cpucfg2 = env->cpucfg[2]; } static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) @@ -205,6 +215,38 @@ static void set_fpr(int reg_num, TCGv val) offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0))); } +static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend) +{ + TCGv temp = NULL; + + if (addend || ctx->va32) { + temp = tcg_temp_new(); + } + if (addend) { + tcg_gen_add_tl(temp, base, addend); + base = temp; + } + if (ctx->va32) { + tcg_gen_ext32u_tl(temp, base); + base = temp; + } + return base; +} + +static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs) +{ + TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL; + return make_address_x(ctx, base, addend); +} + +static uint64_t make_address_pc(DisasContext *ctx, uint64_t addr) +{ + if (ctx->va32) { + addr = (int32_t)addr; + } + return addr; +} + #include "decode-insns.c.inc" #include "insn_trans/trans_arith.c.inc" #include "insn_trans/trans_shift.c.inc" @@ -236,6 +278,10 @@ static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) } ctx->base.pc_next += 4; + + if (ctx->va32) { + ctx->base.pc_next = (uint32_t)ctx->base.pc_next; + } } static void loongarch_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 7f60090580..89b49a859e 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -10,9 +10,20 @@ #include "exec/translator.h" -#define TRANS(NAME, FUNC, ...) \ +#define TRANS(NAME, AVAIL, FUNC, ...) \ static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ - { return FUNC(ctx, a, __VA_ARGS__); } + { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } + +#define avail_ALL(C) true +#define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \ + CPUCFG1_ARCH_LA64) +#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP)) +#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP)) +#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP)) +#define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW)) +#define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM)) +#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX)) +#define avail_IOCSR(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, IOCSR)) /* * If an operation is being performed on less than TARGET_LONG_BITS, @@ -33,6 +44,10 @@ typedef struct DisasContext { uint16_t plv; int vl; /* Vector length */ TCGv zero; + bool la64; /* LoongArch64 mode */ + bool va32; /* 32-bit virtual address */ + uint32_t cpucfg1; + uint32_t cpucfg2; } DisasContext; void generate_exception(DisasContext *ctx, int excp); |