diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-06-21 16:23:02 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-06-21 18:09:54 +0200 |
| commit | a9c37abdff65a07d0191123a21d318c4d8cc7f33 (patch) | |
| tree | 796f1e93b199bf825f741cff4baa167b8e595f32 /target/tricore | |
| parent | 19a18edd8860064d3dbe71bc5315347bcfeb4c24 (diff) | |
target/tricore: Fix ICR.IE offset in RESTORE insn
from ISA v1.6.1 onwards the bit position of ICR.IE changed.
ctx->icr_ie_offset contains the correct value for the ISA version used
by the vCPU. We also need to exit this tb here, as we might have enabled
interrupts.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-Id: <20230621142302.1648383-9-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore')
| -rw-r--r-- | target/tricore/translate.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 9e408f44ec..2f32463d4d 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -7964,7 +7964,9 @@ static void decode_sys_interrupts(DisasContext *ctx) case OPC2_32_SYS_RESTORE: if (has_feature(ctx, TRICORE_FEATURE_16)) { if (ctx->priv == TRICORE_PRIV_SM || ctx->priv == TRICORE_PRIV_UM1) { - tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], 8, 1); + tcg_gen_deposit_tl(cpu_ICR, cpu_ICR, cpu_gpr_d[r1], + ctx->icr_ie_offset, 1); + ctx->base.is_jmp = DISAS_EXIT_UPDATE; } else { generate_trap(ctx, TRAPC_PROT, TIN1_PRIV); } |