diff options
| author | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-08-28 13:26:49 +0200 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2023-09-28 10:45:22 +0200 |
| commit | 222ff2d3581e46731fe19644dfc4c4f36f39ac03 (patch) | |
| tree | baa238121a8fdc1b19201d32ccffc7fda117f1e3 /target/tricore/translate.c | |
| parent | 23fa6f56b33f8fddf86ba4d027fb7d3081440cd9 (diff) | |
target/tricore: Swap src and dst reg for RCRR_INSERT
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Message-ID: <20230828112651.522058-10-kbastian@mail.uni-paderborn.de>
Diffstat (limited to 'target/tricore/translate.c')
| -rw-r--r-- | target/tricore/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 3f950ae33b..7aba7b067c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -8223,12 +8223,12 @@ static void decode_32Bit_opc(DisasContext *ctx) temp2 = tcg_temp_new(); /* width*/ temp3 = tcg_temp_new(); /* pos */ - CHECK_REG_PAIR(r3); + CHECK_REG_PAIR(r2); - tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f); - tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f); + tcg_gen_andi_tl(temp2, cpu_gpr_d[r2 + 1], 0x1f); + tcg_gen_andi_tl(temp3, cpu_gpr_d[r2], 0x1f); - gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3); + gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, temp2, temp3); break; /* RCRW Format */ case OPCM_32_RCRW_MASK_INSERT: |