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authorGeorg Kotheimer <georg.kotheimer@kernkonzept.com>2020-10-13 19:22:23 +0200
committerAlistair Francis <alistair.francis@wdc.com>2020-10-22 12:00:22 -0700
commit1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa (patch)
tree10470a252045e34f111eacae67b8d12095138024 /target/riscv
parent4aeb9e26c219a85f465eb2cc7ef6939a3c71944f (diff)
target/riscv: Fix implementation of HLVX.WU instruction
The HLVX.WU instruction is supposed to read a machine word, but prior to this change it read a byte instead. Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions") Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201013172223.443645-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv')
-rw-r--r--target/riscv/op_helper.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e987bd262f..4ce73575a7 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -333,12 +333,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
riscv_cpu_set_two_stage_lookup(env, true);
switch (memop) {
- case MO_TEUL:
- pte = cpu_ldub_data_ra(env, address, GETPC());
- break;
case MO_TEUW:
pte = cpu_lduw_data_ra(env, address, GETPC());
break;
+ case MO_TEUL:
+ pte = cpu_ldl_data_ra(env, address, GETPC());
+ break;
default:
g_assert_not_reached();
}