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authorLIU Zhiwei <zhiwei_liu@c-sky.com>2022-01-20 20:20:42 +0800
committerAlistair Francis <alistair.francis@wdc.com>2022-01-21 15:52:57 +1000
commitd96a271a8daedb83247baf89349ead0cb8f0c449 (patch)
treed65c84edeaa22dcedd48cd16a6e042b89187a9e7 /target/riscv/vector_helper.c
parent4208dc7e9e6fe1bb7a0698eac31f44388046dc00 (diff)
target/riscv: Split out the vill from vtype
We need not specially process vtype when XLEN changes. Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220120122050.41546-16-zhiwei_liu@c-sky.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'target/riscv/vector_helper.c')
-rw-r--r--target/riscv/vector_helper.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ad505ec9b2..a9484c22ea 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -52,7 +52,8 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
|| (ediv != 0)
|| (reserved != 0)) {
/* only set vill bit. */
- env->vtype = FIELD_DP64(0, VTYPE, VILL, 1);
+ env->vill = 1;
+ env->vtype = 0;
env->vl = 0;
env->vstart = 0;
return 0;