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authorBastian Koppelmann <kbastian@mail.uni-paderborn.de>2019-02-13 07:54:04 -0800
committerBastian Koppelmann <kbastian@mail.uni-paderborn.de>2019-03-13 10:40:50 +0100
commitf2ab1728675772cd475a33f4df3d2f68a22c188f (patch)
treed8cb7a661ff862fed7197f5d4125268d3896ccb6 /target/riscv/insn_trans/trans_rvi.inc.c
parent7a50d3e2ae7f13b24fe55990ea0b8ddcbbb43130 (diff)
target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
manual decoding in gen_arith() is not necessary with decodetree. For now the function is called trans_arith as the original gen_arith still exists. The former will be renamed to gen_arith as soon as the old gen_arith can be removed. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Peer Adelt <peer.adelt@hni.uni-paderborn.de>
Diffstat (limited to 'target/riscv/insn_trans/trans_rvi.inc.c')
-rw-r--r--target/riscv/insn_trans/trans_rvi.inc.c21
1 files changed, 7 insertions, 14 deletions
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.inc.c
index 0265740bdb..8879f2da35 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -312,14 +312,12 @@ static bool trans_srai(DisasContext *ctx, arg_srai *a)
static bool trans_add(DisasContext *ctx, arg_add *a)
{
- gen_arith(ctx, OPC_RISC_ADD, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_add_tl);
}
static bool trans_sub(DisasContext *ctx, arg_sub *a)
{
- gen_arith(ctx, OPC_RISC_SUB, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_sub_tl);
}
static bool trans_sll(DisasContext *ctx, arg_sll *a)
@@ -342,8 +340,7 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
static bool trans_xor(DisasContext *ctx, arg_xor *a)
{
- gen_arith(ctx, OPC_RISC_XOR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_xor_tl);
}
static bool trans_srl(DisasContext *ctx, arg_srl *a)
@@ -360,14 +357,12 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
static bool trans_or(DisasContext *ctx, arg_or *a)
{
- gen_arith(ctx, OPC_RISC_OR, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_or_tl);
}
static bool trans_and(DisasContext *ctx, arg_and *a)
{
- gen_arith(ctx, OPC_RISC_AND, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &tcg_gen_and_tl);
}
#ifdef TARGET_RISCV64
@@ -414,14 +409,12 @@ static bool trans_sraiw(DisasContext *ctx, arg_sraiw *a)
static bool trans_addw(DisasContext *ctx, arg_addw *a)
{
- gen_arith(ctx, OPC_RISC_ADDW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_addw);
}
static bool trans_subw(DisasContext *ctx, arg_subw *a)
{
- gen_arith(ctx, OPC_RISC_SUBW, a->rd, a->rs1, a->rs2);
- return true;
+ return trans_arith(ctx, a, &gen_subw);
}
static bool trans_sllw(DisasContext *ctx, arg_sllw *a)