diff options
author | Bin Meng <bin.meng@windriver.com> | 2021-02-10 10:45:52 +0800 |
---|---|---|
committer | David Gibson <david@gibson.dropbear.id.au> | 2021-02-10 14:50:11 +1100 |
commit | 298091f831db1a8f360686369f9760849e90dd03 (patch) | |
tree | 146281fe319fe57755b884f700356918a01946dd /target/ppc/cpu.h | |
parent | ce8e43760e8e7e08c3ab11af874db404d9419a27 (diff) |
target/ppc: Add E500 L2CSR0 write helper
Per EREF 2.0 [1] chapter 3.11.2:
The following bits in L2CSR0 (exists in the e500mc/e5500/e6500 core):
- L2FI (L2 cache flash invalidate)
- L2FL (L2 cache flush)
- L2LFC (L2 cache lock flash clear)
when set, a cache operation is initiated by hardware, and these bits
will be cleared when the operation is complete.
Since we don't model cache in QEMU, let's add a write helper to emulate
the cache operations completing instantly.
[1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREFRM.pdf
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Message-Id: <1612925152-20913-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'target/ppc/cpu.h')
-rw-r--r-- | target/ppc/cpu.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index cb00210288..e73416da68 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1919,6 +1919,7 @@ typedef PowerPCCPU ArchCPU; #define SPR_750FX_HID2 (0x3F8) #define SPR_Exxx_L1FINV0 (0x3F8) #define SPR_L2CR (0x3F9) +#define SPR_Exxx_L2CSR0 (0x3F9) #define SPR_L3CR (0x3FA) #define SPR_750_TDCH (0x3FA) #define SPR_IABR2 (0x3FA) @@ -1974,6 +1975,11 @@ typedef PowerPCCPU ArchCPU; #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ +/* E500 L2CSR0 */ +#define E500_L2CSR0_L2FI (1 << 21) /* L2 cache flash invalidate */ +#define E500_L2CSR0_L2FL (1 << 11) /* L2 cache flush */ +#define E500_L2CSR0_L2LFC (1 << 10) /* L2 cache lock flash clear */ + /* HID0 bits */ #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */ #define HID0_DOZE (1 << 23) /* pre-2.06 */ |