diff options
| author | Richard Henderson <richard.henderson@linaro.org> | 2019-08-25 15:44:11 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2019-09-04 12:53:10 -0700 |
| commit | fe636d3722bf266c7b1bd3ca12fa53fb78ceffa0 (patch) | |
| tree | 63bda0699b1e08f4394f9fb1a23bef8febbd9f34 /target/openrisc/cpu.c | |
| parent | 091a35165f206718ecce1f0ddf42563b81086170 (diff) | |
target/openrisc: Check CPUCFG_OF32S for float insns
Make sure the OF32S insns are enabled before allowing execution.
Include the missing bit for cpu "any".
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 9f566ad883..f3c8134531 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -131,7 +131,7 @@ static void openrisc_any_initfn(Object *obj) cpu->env.avr = 0x01010000; /* Architecture v1.1 */ cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | UPR_PMP; - cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | + cpu->env.cpucfgr = CPUCFGR_NSGF | CPUCFGR_OB32S | CPUCFGR_OF32S | CPUCFGR_AVRP | CPUCFGR_EVBARP; /* 1Way, TLB_SIZE entries. */ |