diff options
| author | Stafford Horne <shorne@gmail.com> | 2017-04-24 06:07:42 +0900 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2017-05-04 09:39:14 +0900 |
| commit | f4d1414a9385e3375d9107b29eeb75d27daf2147 (patch) | |
| tree | 91182987a6331fc44772a6179e170163b9635706 /target/openrisc/cpu.c | |
| parent | 48a1b62baaf45e4d8d5ffac77647f7e898d7f7f1 (diff) | |
target/openrisc: Support non-busy idle state using PMR SPR
The OpenRISC architecture has the Power Management Register (PMR)
special purpose register to manage cpu power states. The interesting
modes are:
* Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt
* Sleep Mode (SME) - Stop cpu and all units - wake on interrupt
* Suspend Model (SUME) - Stop cpu and all units - wake on reset
The linux kernel will set DME when idle.
This patch implements the PMR SPR and halts the qemu cpu when there is a
change to DME or SME. This means that openrisc qemu in no longer peggs
a host cpu at 100%.
In order for this to work we need to kick the CPU when timers are
expired. Update the cpu timer to kick the cpu upon each timer event.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'target/openrisc/cpu.c')
| -rw-r--r-- | target/openrisc/cpu.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index c9b3f2260e..1d6330cbcc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -51,7 +51,8 @@ static void openrisc_cpu_reset(CPUState *s) cpu->env.lock_addr = -1; s->exception_index = -1; - cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP; + cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP | + UPR_PMP; cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2)); cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2)); |