diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-19 18:29:14 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-11-02 14:32:32 +0100 |
| commit | 6f74237691461fb2f875aecb35a92a073d0bb7fb (patch) | |
| tree | 966141d8f3410ad5bf7e46000d1827419244493e /target/mips | |
| parent | 62ba0e855a0ffe90142de9b6aac0e89ab8c0b894 (diff) | |
target/mips: Convert CFCMSA opcode to decodetree
Convert the CFCMSA (Copy From Control MSA register) opcode
to decodetree. Since it overlaps with the SPLATI opcode,
use a decodetree overlap group.
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-29-f4bug@amsat.org>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/tcg/msa.decode | 5 | ||||
| -rw-r--r-- | target/mips/tcg/msa_translate.c | 27 |
2 files changed, 23 insertions, 9 deletions
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode index d1b6a63b52..de8153a89b 100644 --- a/target/mips/tcg/msa.decode +++ b/target/mips/tcg/msa.decode @@ -168,7 +168,10 @@ BNZ 010001 111 .. ..... ................ @bz HSUB_U 011110 111.. ..... ..... ..... 010101 @3r SLDI 011110 0000 ...... ..... ..... 011001 @elm_df - SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + { + CFCMSA 011110 0001111110 ..... ..... 011001 @elm + SPLATI 011110 0001 ...... ..... ..... 011001 @elm_df + } { MOVE_V 011110 0010111110 ..... ..... 011001 @elm COPY_S 011110 0010 ...... ..... ..... 011001 @elm_df diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index ea572413ed..764b33741a 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -45,7 +45,6 @@ enum { enum { /* ELM instructions df(bits 21..16) = _b, _h, _w, _d */ OPC_CTCMSA = (0x0 << 22) | (0x3E << 16) | OPC_MSA_ELM, - OPC_CFCMSA = (0x1 << 22) | (0x3E << 16) | OPC_MSA_ELM, }; static const char msaregnames[][6] = { @@ -551,7 +550,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) uint8_t source = (ctx->opcode >> 11) & 0x1f; uint8_t dest = (ctx->opcode >> 6) & 0x1f; TCGv telm = tcg_temp_new(); - TCGv_i32 tsr = tcg_const_i32(source); TCGv_i32 tdt = tcg_const_i32(dest); switch (MASK_MSA_ELM_DF3E(ctx->opcode)) { @@ -559,10 +557,6 @@ static void gen_msa_elm_3e(DisasContext *ctx) gen_load_gpr(telm, source); gen_helper_msa_ctcmsa(cpu_env, telm, tdt); break; - case OPC_CFCMSA: - gen_helper_msa_cfcmsa(telm, cpu_env, tsr); - gen_store_gpr(telm, dest); - break; default: MIPS_INVAL("MSA instruction"); gen_reserved_instruction(ctx); @@ -571,7 +565,24 @@ static void gen_msa_elm_3e(DisasContext *ctx) tcg_temp_free(telm); tcg_temp_free_i32(tdt); - tcg_temp_free_i32(tsr); +} + +static bool trans_CFCMSA(DisasContext *ctx, arg_msa_elm *a) +{ + TCGv telm; + + if (!check_msa_enabled(ctx)) { + return true; + } + + telm = tcg_temp_new(); + + gen_helper_msa_cfcmsa(telm, cpu_env, tcg_constant_i32(a->ws)); + gen_store_gpr(telm, a->wd); + + tcg_temp_free(telm); + + return true; } static bool trans_msa_elm(DisasContext *ctx, arg_msa_elm_df *a, @@ -663,7 +674,7 @@ static void gen_msa_elm(DisasContext *ctx) uint8_t dfn = (ctx->opcode >> 16) & 0x3f; if (dfn == 0x3E) { - /* CTCMSA, CFCMSA */ + /* CTCMSA */ gen_msa_elm_3e(ctx); return; } else { |