diff options
| author | Yongbok Kim <yongbok.kim@mips.com> | 2018-08-02 16:16:09 +0200 |
|---|---|---|
| committer | Aleksandar Markovic <amarkovic@wavecomp.com> | 2018-08-24 17:51:59 +0200 |
| commit | 8869ad02bfd9737f6a8fceab5ca286eaa899b790 (patch) | |
| tree | 9cf5c5494156192f204c8203aca272284b9a2e4a /target/mips | |
| parent | c46562fb2fd41429c7acbf10dedfd5cbe0aa34fa (diff) | |
target/mips: Add emulation of nanoMIPS 16-bit misc instructions
Add emulation of misc nanoMIPS 16-bit instructions.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Yongbok Kim <yongbok.kim@mips.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Stefan Markovic <smarkovic@wavecomp.com>
Diffstat (limited to 'target/mips')
| -rw-r--r-- | target/mips/translate.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index e3fac1ab0b..c774dc9e42 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -16763,6 +16763,40 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) op = extract32(ctx->opcode, 10, 6); switch (op) { case NM_P16_MV: + rt = NANOMIPS_EXTRACT_RD5(ctx->opcode); + if (rt != 0) { + /* MOVE */ + rs = NANOMIPS_EXTRACT_RS5(ctx->opcode); + gen_arith(ctx, OPC_ADDU, rt, rs, 0); + } else { + /* P16.RI */ + switch (extract32(ctx->opcode, 3, 2)) { + case NM_P16_SYSCALL: + if (extract32(ctx->opcode, 2, 1) == 0) { + generate_exception_end(ctx, EXCP_SYSCALL); + } else { + generate_exception_end(ctx, EXCP_RI); + } + break; + case NM_BREAK16: + generate_exception_end(ctx, EXCP_BREAK); + break; + case NM_SDBBP16: + if (is_uhi(extract32(ctx->opcode, 0, 3))) { + gen_helper_do_semihosting(cpu_env); + } else { + if (ctx->hflags & MIPS_HFLAG_SBRI) { + generate_exception_end(ctx, EXCP_RI); + } else { + generate_exception_end(ctx, EXCP_DBp); + } + } + break; + default: + generate_exception_end(ctx, EXCP_RI); + break; + } + } break; case NM_P16_SHIFT: { @@ -16842,6 +16876,13 @@ static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx) } break; case NM_LI16: + { + int imm = extract32(ctx->opcode, 0, 7); + imm = (imm == 0x7f ? -1 : imm); + if (rt != 0) { + tcg_gen_movi_tl(cpu_gpr[rt], imm); + } + } break; case NM_ANDI16: break; |