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author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2020-11-29 22:24:40 +0100 |
---|---|---|
committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-01-14 17:13:53 +0100 |
commit | c7a9ef75173f090616328d6870f71e8da2b6bd50 (patch) | |
tree | c8ff947fcff0722228df080d8fc38e6610b772a0 /target/mips/msa_translate.c | |
parent | 878b87b54176d7cea4a74ec544703e408776ed34 (diff) |
target/mips: Introduce decode tree bindings for MSA ASE
Introduce the 'msa32' decodetree config for the 32-bit MSA ASE.
We start by decoding:
- the branch instructions,
- all instructions based on the MSA opcode.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201215225757.764263-20-f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Tested-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Diffstat (limited to 'target/mips/msa_translate.c')
-rw-r--r-- | target/mips/msa_translate.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/target/mips/msa_translate.c b/target/mips/msa_translate.c index 52bd428759..5efb0a1fc8 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/msa_translate.c @@ -6,6 +6,7 @@ * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) + * Copyright (c) 2020 Philippe Mathieu-Daudé * * SPDX-License-Identifier: LGPL-2.1-or-later */ @@ -16,6 +17,9 @@ #include "fpu_helper.h" #include "internal.h" +/* Include the auto-generated decoder. */ +#include "decode-msa32.c.inc" + #define OPC_MSA (0x1E << 26) #define MASK_MSA_MINOR(op) (MASK_OP_MAJOR(op) | (op & 0x3F)) @@ -370,6 +374,16 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond) return true; } +static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ); +} + +static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE); +} + static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) { check_msa_access(ctx); @@ -388,6 +402,16 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool if_not) return true; } +static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false); +} + +static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a) +{ + return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true); +} + void gen_msa_branch(DisasContext *ctx, uint32_t op1) { uint8_t df = (ctx->opcode >> 21) & 0x3; @@ -2261,3 +2285,15 @@ void gen_msa(DisasContext *ctx) break; } } + +static bool trans_MSA(DisasContext *ctx, arg_MSA *a) +{ + gen_msa(ctx); + + return true; +} + +bool decode_ase_msa(DisasContext *ctx, uint32_t insn) +{ + return decode_msa32(ctx, insn); +} |