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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-19 22:37:40 -0700 |
|---|---|---|
| committer | Richard Henderson <richard.henderson@linaro.org> | 2020-09-01 07:41:38 -0700 |
| commit | 6efd55995a224787baa712500b82ef21a148d38e (patch) | |
| tree | 6d34b48064a7c5b6527062ac2725ca4185a34713 /target/microblaze/helper.c | |
| parent | 3e0e16ae1e0048a21a91674061ec9c43c5d7a76c (diff) | |
target/microblaze: Fix width of ESR
The exception status register is only 32-bits wide.
Do not use a 64-bit type to represent it.
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/microblaze/helper.c')
| -rw-r--r-- | target/microblaze/helper.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index af79091fd2..b2373f6a23 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -144,7 +144,7 @@ void mb_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "hw exception at pc=%x ear=%" PRIx64 " " - "esr=%" PRIx64 " iflags=%x\n", + "esr=%x iflags=%x\n", env->pc, env->ear, env->esr, env->iflags); log_cpu_state_mask(CPU_LOG_INT, cs, 0); |