diff options
author | Song Gao <gaosong@loongson.cn> | 2023-05-04 20:28:06 +0800 |
---|---|---|
committer | Song Gao <gaosong@loongson.cn> | 2023-05-06 11:19:49 +0800 |
commit | e93dd43147351290ec1eac83e04cfc0a7f641d63 (patch) | |
tree | c148956f26f12c5de2c50b7126b8d52ab68127f1 /target/loongarch/insns.decode | |
parent | d5e5563cb376061e8d2ded74c0212f3f307eb2f9 (diff) |
target/loongarch: Implement vilvl vilvh vextrins vshuf
This patch includes:
- VILV{L/H}.{B/H/W/D};
- VSHUF.{B/H/W/D};
- VSHUF4I.{B/H/W/D};
- VPERMI.W;
- VEXTRINS.{B/H/W/D}.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-Id: <20230504122810.4094787-41-gaosong@loongson.cn>
Diffstat (limited to 'target/loongarch/insns.decode')
-rw-r--r-- | target/loongarch/insns.decode | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode index ab9e9e422f..0263bce28e 100644 --- a/target/loongarch/insns.decode +++ b/target/loongarch/insns.decode @@ -1231,3 +1231,28 @@ vpickod_b 0111 00010010 00000 ..... ..... ..... @vvv vpickod_h 0111 00010010 00001 ..... ..... ..... @vvv vpickod_w 0111 00010010 00010 ..... ..... ..... @vvv vpickod_d 0111 00010010 00011 ..... ..... ..... @vvv + +vilvl_b 0111 00010001 10100 ..... ..... ..... @vvv +vilvl_h 0111 00010001 10101 ..... ..... ..... @vvv +vilvl_w 0111 00010001 10110 ..... ..... ..... @vvv +vilvl_d 0111 00010001 10111 ..... ..... ..... @vvv +vilvh_b 0111 00010001 11000 ..... ..... ..... @vvv +vilvh_h 0111 00010001 11001 ..... ..... ..... @vvv +vilvh_w 0111 00010001 11010 ..... ..... ..... @vvv +vilvh_d 0111 00010001 11011 ..... ..... ..... @vvv + +vshuf_b 0000 11010101 ..... ..... ..... ..... @vvvv +vshuf_h 0111 00010111 10101 ..... ..... ..... @vvv +vshuf_w 0111 00010111 10110 ..... ..... ..... @vvv +vshuf_d 0111 00010111 10111 ..... ..... ..... @vvv +vshuf4i_b 0111 00111001 00 ........ ..... ..... @vv_ui8 +vshuf4i_h 0111 00111001 01 ........ ..... ..... @vv_ui8 +vshuf4i_w 0111 00111001 10 ........ ..... ..... @vv_ui8 +vshuf4i_d 0111 00111001 11 ........ ..... ..... @vv_ui8 + +vpermi_w 0111 00111110 01 ........ ..... ..... @vv_ui8 + +vextrins_d 0111 00111000 00 ........ ..... ..... @vv_ui8 +vextrins_w 0111 00111000 01 ........ ..... ..... @vv_ui8 +vextrins_h 0111 00111000 10 ........ ..... ..... @vv_ui8 +vextrins_b 0111 00111000 11 ........ ..... ..... @vv_ui8 |