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authorRichard Henderson <richard.henderson@linaro.org>2023-10-27 02:46:44 -0700
committerRichard Henderson <richard.henderson@linaro.org>2023-11-06 18:49:34 -0800
commitf5b5c85760c6d3cf073d8e0ee85d170c569d3ddf (patch)
tree62ce244e265edd4639055a7def20186ba82b8ef6 /target/hppa/translate.c
parent4c34bab0d3dc59fef4ebce831fbca784a1e3e06a (diff)
target/hppa: Add unwind_breg to CPUHPPAState
Fill in the insn_start value during form_gva, and copy it out to the env field in hppa_restore_state_to_opc. The value is not yet consumed. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/translate.c')
-rw-r--r--target/hppa/translate.c13
1 files changed, 12 insertions, 1 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4102f5faf3..bcce65d587 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -44,6 +44,7 @@ typedef struct DisasCond {
typedef struct DisasContext {
DisasContextBase base;
CPUState *cs;
+ TCGOp *insn_start;
uint64_t iaoq_f;
uint64_t iaoq_b;
@@ -234,6 +235,13 @@ void hppa_translate_init(void)
"iasq_b");
}
+static void set_insn_breg(DisasContext *ctx, int breg)
+{
+ assert(ctx->insn_start != NULL);
+ tcg_set_insn_start_param(ctx->insn_start, 2, breg);
+ ctx->insn_start = NULL;
+}
+
static DisasCond cond_make_f(void)
{
return (DisasCond){
@@ -1324,6 +1332,8 @@ static void form_gva(DisasContext *ctx, TCGv_i64 *pgva, TCGv_i64 *pofs,
TCGv_i64 ofs;
TCGv_i64 addr;
+ set_insn_breg(ctx, rb);
+
/* Note that RX is mutually exclusive with DISP. */
if (rx) {
ofs = tcg_temp_new_i64();
@@ -4458,7 +4468,8 @@ static void hppa_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b);
+ tcg_gen_insn_start(ctx->iaoq_f, ctx->iaoq_b, 0);
+ ctx->insn_start = tcg_last_op();
}
static void hppa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)