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authorRichard Henderson <richard.henderson@linaro.org>2024-03-02 15:10:00 -1000
committerRichard Henderson <richard.henderson@linaro.org>2024-03-19 13:33:39 -1000
commit72bace2d13cb427fde3bb50ae1a71a2abe9acc0f (patch)
tree017cd7149f3250088b77950217eef76edc00ecf3 /target/hppa/translate.c
parentc62d54d0a8067ffb3d5b909276f7296d7df33fa7 (diff)
target/hppa: Fix assemble_16 insns for wide mode
Reported-by: Sven Schnelle <svens@stackframe.org> Reviewed-by: Helge Deller <deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Diffstat (limited to 'target/hppa/translate.c')
-rw-r--r--target/hppa/translate.c22
1 files changed, 22 insertions, 0 deletions
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index eb2046c5ad..cbe44ef75a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -144,6 +144,28 @@ static int assemble_6(DisasContext *ctx, int val)
return (val ^ 31) + 1;
}
+/* Expander for assemble_16(s,im14). */
+static int expand_16(DisasContext *ctx, int val)
+{
+ /*
+ * @val is bits [0:15], containing both im14 and s.
+ * Swizzle thing around depending on PSW.W.
+ */
+ int s = extract32(val, 14, 2);
+ int i = (-(val & 1) << 13) | extract32(val, 1, 13);
+
+ if (ctx->tb_flags & PSW_W) {
+ i ^= s << 13;
+ }
+ return i;
+}
+
+/* The sp field is only present with !PSW_W. */
+static int sp0_if_wide(DisasContext *ctx, int sp)
+{
+ return ctx->tb_flags & PSW_W ? 0 : sp;
+}
+
/* Translate CMPI doubleword conditions to standard. */
static int cmpbid_c(DisasContext *ctx, int val)
{