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authorPeter Maydell <peter.maydell@linaro.org>2017-01-20 11:15:09 +0000
committerPeter Maydell <peter.maydell@linaro.org>2017-01-20 11:15:09 +0000
commit5454006a7cc6caf10c1816e6828b75a40fbcc16e (patch)
treef949eacfd3e98d6b55211069d1b079b4ca52543b /target/arm
parentaa1b3111b3f3c53b9290ecade02f31acfc579c16 (diff)
hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU
Wire the new VIRQ, VFIQ and maintenance interrupt lines from the GIC to each CPU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1483977924-14522-5-git-send-email-peter.maydell@linaro.org
Diffstat (limited to 'target/arm')
0 files changed, 0 insertions, 0 deletions