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| author | Richard Henderson <richard.henderson@linaro.org> | 2020-08-28 10:02:50 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2020-08-28 10:02:50 +0100 |
| commit | 2e5a265e6a9e7169c4a3e87db261b2fa92582590 (patch) | |
| tree | 2c76b11d5eada82a390222aad999704fd1453641 /target/arm/translate-a64.c | |
| parent | d21798856b227a20a0a41640236af445f4f4aeb0 (diff) | |
target/arm: Convert integer multiply (indexed) to gvec for aa64 advsimd
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200815013145.539409-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/translate-a64.c')
| -rw-r--r-- | target/arm/translate-a64.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 115dc946e7..abbd6421a2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13488,6 +13488,22 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) data, gen_helper_gvec_fmlal_idx_a64); } return; + + case 0x08: /* MUL */ + if (!is_long && !is_scalar) { + static gen_helper_gvec_3 * const fns[3] = { + gen_helper_gvec_mul_idx_h, + gen_helper_gvec_mul_idx_s, + gen_helper_gvec_mul_idx_d, + }; + tcg_gen_gvec_3_ool(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s), + index, fns[size - 1]); + return; + } + break; } if (size == 3) { |