diff options
| author | Philippe Mathieu-Daudé <philmd@redhat.com> | 2019-07-01 17:26:20 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2019-07-01 17:29:01 +0100 |
| commit | ebae861fc6c385a7bcac72dde4716be06e6776f1 (patch) | |
| tree | 4f5711808405c9c699aac00d9ad7500856fa37b9 /target/arm/internals.h | |
| parent | 864806156a0e48255331636b3550bcbf2bd2d3d6 (diff) | |
target/arm: Declare get_phys_addr() function publicly
In the next commit we will split the TLB related routines of
this file, and this function will also be called in the new
file. Declare it in the "internals.h" header.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190701132516.26392-12-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
| -rw-r--r-- | target/arm/internals.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h index 5a02f458f3..ff5ab0328e 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -985,4 +985,20 @@ static inline int exception_target_el(CPUARMState *env) return target_el; } +#ifndef CONFIG_USER_ONLY + +/* Cacheability and shareability attributes for a memory access */ +typedef struct ARMCacheAttrs { + unsigned int attrs:8; /* as in the MAIR register encoding */ + unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PTEs */ +} ARMCacheAttrs; + +bool get_phys_addr(CPUARMState *env, target_ulong address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi, ARMCacheAttrs *cacheattrs); + +#endif /* !CONFIG_USER_ONLY */ + #endif |