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authorRichard Henderson <richard.henderson@linaro.org>2020-06-25 20:31:31 -0700
committerPeter Maydell <peter.maydell@linaro.org>2020-06-26 14:31:12 +0100
commit206adacfb8d35e671e3619591608c475aa046b63 (patch)
tree44ed93ca28ab3c527316dc4fcc1d680bd3600b63 /target/arm/internals.h
parent149d3b31f3f0f7f9e1c3a77043450a95c7a7e93d (diff)
target/arm: Add mte helpers for sve scalar + int loads
Because the elements are sequential, we can eliminate many tests all at once when the tag hits TCMA, or if the page(s) are not Tagged. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/internals.h')
-rw-r--r--target/arm/internals.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/target/arm/internals.h b/target/arm/internals.h
index c763a23dfb..3306c4f829 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1310,6 +1310,12 @@ void arm_log_exception(int idx);
#define LOG2_TAG_GRANULE 4
#define TAG_GRANULE (1 << LOG2_TAG_GRANULE)
+/*
+ * The SVE simd_data field, for memory ops, contains either
+ * rd (5 bits) or a shift count (2 bits).
+ */
+#define SVE_MTEDESC_SHIFT 5
+
/* Bits within a descriptor passed to the helper_mte_check* functions. */
FIELD(MTEDESC, MIDX, 0, 4)
FIELD(MTEDESC, TBI, 4, 2)