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| author | Alex Bennée <alex.bennee@linaro.org> | 2018-03-01 11:05:48 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-03-01 11:13:59 +0000 |
| commit | 807cdd504283c11addcd7ea95ba594bbddc86fe4 (patch) | |
| tree | aea3cddf23b332791785f3c23668f268ddab096d /target/arm/helper-a64.h | |
| parent | 9b04991686785e18b18a36d193b68f08f7c91648 (diff) | |
arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV)
This implements the half-precision variants of the across vector
reduction operations. This involves a re-factor of the reduction code
which more closely matches the ARM ARM order (and handles 8 element
reductions).
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180227143852.11175-7-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'target/arm/helper-a64.h')
| -rw-r--r-- | target/arm/helper-a64.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 85d86741db..cb2a73124d 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -48,3 +48,7 @@ DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) +DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) |